Semiconductor Chip Stacking via Lateral Side-Surface Conductive Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The 3-dimensional multilayer chip structure faces challenges in improving manufacturing efficiency, reducing costs, enhancing reliability, and miniaturization due to difficulties in forming deep through-holes, embedding conductive materials, and ensuring electrical connections between semiconductor chips, which often result in increased costs and reliability issues.
Innovation Solution
A semiconductor device and manufacturing method involving a first semiconductor chip with a thinner substrate and a second semiconductor chip acting as a supporting substrate, where the side surfaces of their respective wiring portions are covered by a conductive layer for electrical connection, allowing for chip stacking and thinning while reducing the need for surface pad electrodes, thus improving efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep through-holes are formed to penetrate through the substrate while securing insulation, then electrical connection between chips is achieved, but manufacturing efficiency deteriorates and costs increase
Solution Approach 1:
The patent transitions from vertical through-hole connections to lateral side-surface connections. The conductive layer is formed on the side surfaces of wiring portions, enabling electrical connection between stacked chips without requiring deep penetration through the substrate thickness, thus resolving the contradiction between connection reliability and manufacturing efficiency
Solution Approach 2:
The electrical connection is segmented into multiple contact points along the side surfaces of the wiring portions. Instead of requiring a single deep through-hole, the connection is divided into multiple lateral contact regions where the conductive layer interfaces with opposing wiring portions, simplifying the manufacturing process while maintaining reliability
2Manufacturing precision
If the substrate is thinned to form small holes, then hole formation becomes feasible, but additional processes such as bonding to supporting substrate are required, increasing costs
Solution Approach 1:
The patent avoids thinning the substrate by forming holes through it. Instead, the conductive connections are established laterally on the side surfaces of the wiring portions at the original substrate thickness, eliminating the need for substrate thinning and supporting substrate bonding processes
Solution Approach 2:
Rather than forming holes through the substrate from the surface, the patent inverts the approach by forming conductive layers on the side surfaces of existing wiring portions. This reverses the conventional sequence of operations and eliminates the need for substrate thinning while achieving the same electrical connection function
3Reliability
If conductive material is embedded in high aspect ratio holes, then electrical connection is achieved, but material selection is restricted to materials with excellent covering property such as tungsten
Solution Approach 1:
The patent eliminates high aspect ratio holes by forming conductive layers on lateral side surfaces. This dimensional change from vertical to lateral connections allows the use of various conductive materials with different properties, as the lower aspect ratio geometry accommodates materials like copper, aluminum, and other conductors that would not fill high aspect ratio holes effectively
Solution Approach 2:
The patent changes the geometric parameters of the connection structure from high aspect ratio vertical holes to low aspect ratio lateral surfaces. This parameter change in the connection geometry enables the use of a broader range of conductive materials by reducing the filling and coverage requirements that previously limited material selection
4Reliability
If surface pad electrodes are used for electrical connection, then chip stacking is achieved, but chip size increases and miniaturization becomes difficult
Solution Approach 1:
The patent moves the electrical connection interface from the surface plane to the lateral side surfaces of the wiring portions. This dimensional transition allows connections to be made along the vertical stacking direction rather than requiring additional surface area, enabling chip miniaturization while maintaining reliable electrical connections between stacked chips
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device (1) includes: a first semiconductor chip (100); and a second semiconductor chip (200) that is stacked on the first semiconductor chip (100). The first semiconductor chip (100) includes a first wiring portion (111) of which a side surface is exposed at a side portion of the first semiconductor chip (100). The second semiconductor chip (200) includes a second wiring portion (211) of which a side surface is exposed at a side portion of the second semiconductor chip (200). The respective side surfaces of the first wiring portion (111) and the second wiring portion (211), which are exposed at the side portions of the first semiconductor chip (100) and the second semiconductor chip (200), are covered by a conductive layer (401), and the first wiring portion (111) and the second wiring portion (211) are electrically connected to each other through the conductive layer (401).