Semiconductor Layout Timing Accuracy via Layer-Specific Electrical Properties
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Solution Overview
Problem
Current semiconductor design and manufacturing processes face inaccuracies in timing estimation due to the use of single derived capacitance and resistance values for all conductive layers, leading to inefficiencies and inaccuracies in design optimization.
Innovation Solution
A placement and routing tool that assigns interconnections to specific conductive layers based on their unique resistances and capacitances, allowing for accurate time delay estimation and improved design accuracy by considering the specific characteristics of each layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single derived capacitance and resistance values are used for all conductive layers, then device complexity is reduced, but timing estimation precision deteriorates
Solution Approach 1:
The patent segments the conductive layers into different groups (first group and second group) with distinct capacitance and resistance values. Instead of using a single derived value for all layers, the method assigns specific capacitance values (e.g., first capacitance value for first group, second capacitance value for second group) and resistance values (e.g., first resistance value for first group, second resistance value for second group) to different layer groups, thereby improving timing estimation accuracy while maintaining manageable complexity through systematic categorization.
Solution Approach 2:
The patent applies local quality by assigning different electrical characteristics (capacitance and resistance values) to different conductive layers based on their specific properties. Each conductive layer group receives tailored capacitance and resistance values that reflect its local electrical characteristics, enabling more accurate timing analysis for interconnections on different layers rather than using a uniform approximation for all layers.
2Productivity
If layer assignment is performed before routing, then routing efficiency is improved, but timing analysis accuracy may deteriorate without specific layer characteristics
Solution Approach 1:
The patent performs layer assignment as a preliminary action before routing interconnections. By determining which conductive layer group (first group with first capacitance/resistance values or second group with second capacitance/resistance values) each interconnection will use before actual routing, the method enables early timing estimation using appropriate layer-specific electrical characteristics. This preliminary layer assignment improves subsequent routing efficiency while maintaining timing analysis accuracy through the use of group-specific capacitance and resistance values.
Data Source
AI summary
A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.