Semiconductor Lead Plating for Oxidation Prevention

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Solution Overview

Problem

Conventional semiconductor packages have un plated side surfaces of leads, which react with oxygen, leading to contamination and issues during soldering onto printed circuit boards.

Innovation Solution

A method of singulating and plating the side surfaces of semiconductor packages with a different metallic material, such as tin, silver, or gold, to prevent oxidation and ensure reliable soldering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the side surfaces of leads are left unplated in conventional packages, then the manufacturing process is simpler and cost is reduced, but the lead surfaces oxidize easily and create contamination problems during soldering

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidsoldering reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by plating the side surfaces of leads before the molding process. This advance plating prevents oxidation of the copper leads during subsequent manufacturing and storage steps, ensuring the surfaces remain contamination-free for reliable soldering without adding complex post-processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by selectively plating only the side surfaces of the leads that will be exposed after molding, while leaving other surfaces unplated or differently treated. This targeted approach provides oxidation protection where needed (side surfaces) without unnecessarily complicating the entire manufacturing process.

Inventive Principle:
Principle #3Local quality

2Reliability

If plating material is applied to side surfaces of leads, then oxidation is prevented and soldering reliability is improved, but the manufacturing process becomes more complex and time-consuming

Engineering Contradiction:
Improvesoldering reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the plating operation with the existing manufacturing process flow by integrating it before molding. This combination allows the plating to be performed as part of the standard process sequence rather than as a separate, complex post-processing step, thereby improving reliability without proportionally increasing overall process complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If plating is performed after full cutting of the leadframe, then the exposed side surfaces can be plated, but the cutting operation must be complete through the entire leadframe thickness

Engineering Contradiction:
Improvesurface protectionVSAvoidcutting efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs plating as a preliminary action before the full cutting operation. By plating the side surfaces while the leadframe is still in its uncut or partially cut state, the process ensures surface protection is in place before cutting exposes new surfaces, and avoids the need for additional post-cutting plating steps that would reduce productivity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The plating of side surfaces prevents oxidation, enhancing the soldering process and ensuring the semiconductor packages attach effectively to printed circuit boards without contamination.

Implementation Method 1

plating the exposed side surfaces of the leads with a plating material

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9818676B2Singulation method for semiconductor package with plating on side of connectors
Publication Date: 2017.11.14 UTAC HEADQUARTERS PTE LTD
  • US9818676B2 patent drawing
  • US9818676B2 patent drawing
  • US9818676B2 patent drawing

AI summary

A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.