Semiconductor Lead Terminal Stepped Structure for Flip Chip Reliability
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Solution Overview
Problem
Existing semiconductor devices with wire bonding coupling structures face limitations in size reduction due to interference between the capillary and chip edges during wire bonding, leading to restricted miniaturization, increased risk of solder bridges, and reduced reliability due to decreased terminal contact area and increased terminal coming-off rates.
Innovation Solution
The implementation of a semiconductor device structure with lead terminals having a first and second lower surface, where the distance between adjacent first lower surfaces is longer than between adjacent upper surfaces, allowing for flip chip bonding and reducing the size and thickness while enhancing reliability by preventing solder bridges and terminal detachment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the outer dimensions of the die pad are made smaller and leads are brought close to the semiconductor chip to reduce device size, then the length of each side of the semiconductor device is reduced, but the capillary and chip end interfere with each other during wire bonding
Solution Approach 1:
The patent transitions from wire bonding (which requires lateral space for capillary movement) to flip chip bonding (which bonds vertically from the chip underside), fundamentally changing the bonding dimension and eliminating capillary interference with chip edges
Solution Approach 2:
Instead of bonding wires from the chip top surface outward, the patent inverts the approach by bonding directly from the chip underside to the lead terminals, reversing the bonding direction and enabling compact packaging
2Volume of moving object
If the size of each terminal is reduced to minimize device dimensions, then the area of contact between sealing body and terminal surface is reduced, but terminals become prone to come off from the semiconductor device main body
Solution Approach 1:
The patent extends lead terminals vertically into the sealing body (creating a stepped structure with first and second lower surfaces), increasing the bonding interface area in the vertical dimension while maintaining compact horizontal dimensions
Solution Approach 2:
The patent nests the lead terminals within the sealing body structure, with portions of the terminals embedded in the sealing material, creating a nested configuration that enhances mechanical interlocking and adhesion
3Volume of moving object
If the distance between terminals is reduced to minimize device size, then the compactness is improved, but solder bridges are prone to be formed between terminals during solder mounting
Solution Approach 1:
The patent utilizes the vertical dimension by creating a stepped lead terminal structure where adjacent terminals have different elevation levels, increasing the effective spacing in three-dimensional space while maintaining compact two-dimensional footprint
Solution Approach 2:
The patent creates asymmetric spacing between terminals by forming a stepped structure where lead terminals have different heights relative to the chip, breaking the symmetry that would otherwise lead to uniform minimum spacing and solder bridge formation
Data Source
AI summary
The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof. This makes it possible to suppress the production of a solder bridge when the semiconductor package is solder mounted to a mounting board and to reduce the size and thickness of the semiconductor package and further enhance the reliability of the semiconductor package.