Semiconductor Light Emitting Device Varistor ESD Protection
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Solution Overview
Problem
Semiconductor light emitting devices with chip size package structures face challenges in providing electrostatic discharge (ESD) resistance without compromising downsizing, as existing protection methods can hinder heat dissipation and mounting efficiency.
Innovation Solution
Incorporating a varistor film with nonlinear resistance characteristics between the p-side and n-side electrodes, and using a resin layer with varistor particles to divert surge current away from the semiconductor layer, ensuring ESD protection without affecting the device's size or efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protection element is added to provide ESD resistance, then reliability is improved, but device complexity increases and mounting area efficiency decreases
Solution Approach 1:
The patent combines the protection element with the LED chip itself, integrating the ESD protection function into the semiconductor layer structure. The first and second electrodes are formed directly on different regions of the semiconductor layer, merging the light-emitting function and protection function into a single integrated chip, thereby avoiding additional components and reducing structural complexity
Solution Approach 2:
The semiconductor layer serves multiple functions: it acts as both the light-emitting active region and the protection element for ESD resistance. The first electrode region and second electrode region are both formed on the semiconductor layer, allowing the same substrate to perform dual roles of light emission and electrostatic protection, improving mounting area efficiency
2Reliability
If a protection element is added to provide ESD resistance, then reliability is improved, but the device size increases
Solution Approach 1:
The protection element is merged with the LED chip structure, using the same semiconductor layer and substrate for both light emission and ESD protection. This integration eliminates the need for separate protection components, maintaining compact device dimensions while providing ESD resistance
Solution Approach 2:
The patent utilizes the surface area of the semiconductor layer in different spatial regions to accommodate both the light-emitting area and the electrode regions for ESD protection. By distributing functions across different zones of the same planar space, the device maintains its compact size while integrating multiple functions
3Reliability
If a protection element is added to provide ESD resistance, then reliability is improved, but heat dissipation performance deteriorates
Solution Approach 1:
The protection element is integrated into the semiconductor layer with direct thermal coupling to the heat sink substrate. The electrodes and protection structures share the same thermal pathway as the light-emitting region, ensuring that ESD protection does not create additional thermal resistance or hinder heat dissipation performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects the semiconductor light emitting device from ESD by diverting surge currents through the varistor film and resin layer, maintaining high optical output and heat dissipation while preventing semiconductor layer damage, thus enabling ESD resistance without downsizing constraints.
Implementation Method 1
Incorporating a varistor film with nonlinear resistance characteristics between the p-side and n-side electrodes
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first interconnection section, a second interconnection section, and a varistor film. The semiconductor layer includes a light emitting layer. The first electrode is provided in a emitting region on the second surface. The second electrode is provided in a non-emitting region on the second surface. The first interconnection section is provided on the first electrode and electrically connected to the first electrode. The second interconnection section is provided on the second electrode and on the first electrode and electrically connected to the second electrode. The varistor film is provided in contact with the first electrode and the second interconnection section between the first electrode and the second interconnection section.