Semiconductor Device Single Level Shift Circuit dVdt Noise
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Solution Overview
Problem
Conventional semiconductor devices with two level shift circuits for high-side drive in half-bridge power sources experience malfunctions due to out-of-synch operations caused by characteristic spreads in device elements, leading to dV/dt noise issues, which increase costs and reduce reliability.
Innovation Solution
A semiconductor device utilizing a single level shift circuit for both set and reset signals, combined with pulse modulation and demodulation circuits to convert and transmit data symbols, reducing inter-code interference and enabling high-speed operation while preventing malfunctions from dV/dt noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shift circuits are used, then signal transmission is achieved, but dV/dt noise causes malfunctions
Solution Approach 1:
The patent uses clock-synchronized periodic transmission of signals through the level shift circuit. This controlled periodic action reduces susceptibility to dV/dt noise by ensuring signals are transmitted only at appropriate timing moments, preventing noise-induced malfunctions.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor signal transmission status and adjust timing accordingly. This feedback ensures that set and reset signals are properly synchronized and transmitted only when appropriate, reducing the impact of dV/dt noise on circuit operation.
2Productivity
If conventional techniques are used, then signal transmission is achieved, but inter-code interference reduces operational speed
Solution Approach 1:
The patent employs clock-synchronized periodic transmission of signals, which spaces out signal transmissions in a regular pattern. This reduces inter-code interference by ensuring adequate timing separation between consecutive signals, thereby increasing operational speed without causing signal conflicts.
Data Source
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AI summary
A semiconductor device that performs drive control of a high-potential-side switching element includes: one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level; a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by 2 or more bits and representing a set signal or a reset signal, where 1 bit is defined as a combination of H, L codes forming a pair, and outputs the generated data symbol as an input signal of the level shift circuit; a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift circuit, and generates a level-shifted set signal or reset signal; and a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the level-shifted set signal or reset signal outputted from the pulse demodulation circuit.