Semiconductor Lifetime Region Layout for Low Reverse Recovery Loss
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Solution Overview
Problem
Conventional semiconductor devices with freewheeling diodes face challenges in optimizing carrier lifetime and reverse recovery loss due to lattice defects, leading to suboptimal performance in terms of snapback and forward voltage characteristics.
Innovation Solution
The semiconductor device incorporates a first lifetime region with short carrier lifetime and a second lifetime region with longer carrier lifetime, strategically arranged to adjust carrier lifetimes and reduce lattice defect density, thereby improving conductivity modulation and suppressing snapback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If lattice defects are formed in the semiconductor substrate to adjust carrier lifetime, then carrier lifetime is improved, but reverse recovery loss and snapback characteristics deteriorate
Solution Approach 1:
The semiconductor substrate is divided into multiple lifetime regions (first lifetime region with shorter carrier lifetime and second lifetime region with longer carrier lifetime) with different lattice defect densities. This segmentation allows different areas to have optimized carrier lifetimes, resolving the contradiction between achieving adequate carrier lifetime while minimizing reverse recovery loss.
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different lattice defect densities tailored to their specific functional requirements. The first lifetime region has higher lattice defect density for shorter carrier lifetime, while the second lifetime region has lower lattice defect density for longer carrier lifetime, optimizing both carrier lifetime and reverse recovery characteristics locally.
2Duration of action of moving object
If lattice defects are formed to adjust carrier lifetime, then carrier lifetime is improved, but forward voltage characteristics deteriorate
Solution Approach 1:
The semiconductor substrate is segmented into multiple lifetime regions with different lattice defect densities, allowing optimization of forward voltage characteristics in specific regions while maintaining adequate carrier lifetime overall.
Solution Approach 2:
Regions requiring lower forward voltage are designed with appropriate lattice defect densities to optimize carrier lifetime locally, reducing the energy loss during forward conduction while maintaining the necessary carrier lifetime for device operation.
3Ease of manufacture
If uniform lattice defect density is used throughout the semiconductor substrate, then manufacturing is simplified, but carrier lifetime optimization and snapback suppression are compromised
Solution Approach 1:
The semiconductor substrate is divided into multiple lifetime regions with different lattice defect densities. This segmentation enables optimized carrier lifetime control and snapback suppression in different areas, improving reliability while maintaining reasonable manufacturing complexity through systematic region definition.
Solution Approach 2:
Different regions are assigned specific lattice defect densities according to their functional requirements, allowing optimized carrier lifetime and snapback characteristics in each region while maintaining manufacturing feasibility through standardized region patterns.
Data Source
AI summary
Provided is a semiconductor device including: a semiconductor substrate having a base region of a second conductivity type provided between a drift region and an upper surface of the semiconductor substrate; a first lifetime region arranged in the drift region on a lower surface side of the semiconductor substrate relative to the base region; and a second lifetime region which is arranged to be sandwiched between first lifetime regions including the first lifetime region in a first direction parallel to the upper surface of the semiconductor substrate and in which a carrier lifetime is longer than in the first lifetime region, where a width of the second lifetime region in the first direction is 0.2 times or more a thickness of the first lifetime region in a second direction perpendicular to the upper surface of the semiconductor substrate.