Semiconductor Line Segment Patterning via Isolation Trench Shrinking
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Solution Overview
Problem
Conventional lithography processes, including optical lithography and double patterning techniques, face challenges in achieving precise line-end gaps and tip-to-tip distances, especially at smaller node technologies like 32 nm and 22 nm, due to distortion and line-end shortening issues, which result in increased memory cell area and unmanageable lithographic process windows.
Innovation Solution
A method involving the deposition of a hardmask layer, selective etching of continuous lines, and subsequent patterning with isolation trenches, followed by a shrinking process to reduce trench width, allowing for precise control of line-end gaps through a decoupled lithography exposure and etching steps, enabling smaller line-end gaps and a more manageable process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If optical lithography processes are used to form poly lines, then the manufacturing process is simple, but line-end shortening and corner rounding occur resulting in gap distances greater than designed
Solution Approach 1:
The patent divides the patterning process into two separate exposures: first forming continuous poly lines, then forming isolation segments that create the desired gaps. This segmentation allows each step to be optimized independently, achieving precise gap control without the distortions of conventional single-step lithography.
Solution Approach 2:
The patent performs preliminary action by extending line ends in the first exposure before forming isolation segments in the second exposure. This preliminary extension compensates for anticipated line-end shortening, ensuring the final gap dimensions match the design specifications.
2Manufacturing precision
If line ends are extended in the optical mask to compensate for line-end shortening, then poly line lengths are closer to intended design, but the area required for a memory cell increases
Solution Approach 1:
Instead of extending all line ends uniformly, the patent segments the approach by only extending line ends where isolation segments will be formed later. This selective extension maintains poly line length precision while minimizing the additional area required in memory cells.
Solution Approach 2:
The patent applies local quality by making line end extensions only in specific locations where isolation segments are needed, rather than uniformly across all lines. This localized approach achieves the necessary precision while minimizing overall area increase.
3Manufacturing precision
If double patterning with two separate exposures is used to achieve small line end gaps, then line-end shortening is prevented, but the lithographic process window becomes unmanageable for 32 nm and smaller nodes
Solution Approach 1:
The patent changes critical parameters including using 193nm immersion lithography with specific numerical aperture settings, adjusting photoresist composition and processing conditions, and optimizing etch parameters. These parameter changes enable precise patterning at 32nm and smaller nodes while maintaining a manageable process window.
Solution Approach 2:
The patent employs composite materials including specialized photoresist formulations combined with antireflective coatings, and composite etch chemistries. These composite material systems provide the necessary precision and process stability for advanced node fabrication.
4Manufacturing precision
If isolation segments are printed at 30 nm for 22 nm node technology, then the desired precision is achieved, but sufficient lithographic process margins are not possible with 1.35 NA immersion lithography
Solution Approach 1:
The patent performs preliminary action by forming isolation segments with larger initial dimensions that provide process margins, then using selective removal to achieve the final precise dimensions. This approach builds in safety margins early in the process that are refined later, ensuring both precision and reliability.
Solution Approach 2:
The patent introduces intermediary steps including antireflective coating deposition and selective etching processes that act as mediators between the lithography exposure and final pattern transfer. These intermediary steps provide process control and margins that enable reliable fabrication at 22nm node.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the patterning of line-end gaps as small as 30 nm for 22 nm node technology, achieving smaller line-end gaps and a relaxed lithographic process window, improving the precision and controllability of semiconductor device fabrication.
Implementation Method 1
patterning the photoresist layer with a plurality of isolation trenches via a lithography process
Implementation Method 2
depositing an antireflective coating over remaining portions of the hardmask layer
Data Source
AI summary
A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.