Semiconductor Liner Formation for Leaning-Prone Active Regions

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Solution Overview

Problem

High aspect ratio active regions in semiconductor devices are prone to defects such as leaning, which complicates subsequent processing, decreases productivity, and results in poor electrical characteristics.

Innovation Solution

A method involving the formation of a buffer layer using a first heat treatment process at 520° C. to 580° C., followed by the replacement with a sacrificial layer and subsequent removal to expose the active region, allowing for the formation of a semiconductor liner, thereby preventing leaning and enhancing electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the pitch of active regions is decreased to achieve high integration, then the aspect ratio of active regions increases, but this makes active regions vulnerable to leaning defects

Engineering Contradiction:
Improveintegration densityVSAvoidactive region structural integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

A buffer layer is formed on the active region before subsequent processing steps. This buffer layer is created through preliminary heat treatment that modifies the active region structure in advance, providing mechanical support that prevents leaning defects during later manufacturing processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A buffer layer acts as an intermediary structure between the active region and the surrounding environment. This intermediate layer provides mechanical support and stress distribution, preventing the active region from leaning while maintaining the high aspect ratio required for high integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If heat treatment is performed to form the buffer layer, then leaning prevention is achieved, but additional process steps are required

Engineering Contradiction:
Improveactive region structural integrityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer layer formation process combines multiple functions into a single heat treatment step. The same heat treatment that forms the buffer layer also performs preliminary structure modification, reducing the need for separate process steps while maintaining reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The buffer layer serves multiple functions simultaneously: it prevents leaning defects, provides mechanical support during subsequent processing, and can be integrated with existing heat treatment steps in the manufacturing process, thereby reducing overall process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively prevents leaning of active regions, enabling high integration and excellent electrical characteristics in semiconductor devices.

Implementation Method 1

A buffer layer may be formed on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C.

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Data Source

PatentUS20240371701A1Method of forming semiconductor device including semiconductor liner
Publication Date: 2024.11.07 SK HYNIX INC
  • US20240371701A1 patent drawing
  • US20240371701A1 patent drawing
  • US20240371701A1 patent drawing

AI summary

A method for forming a semiconductor device may include forming, on a substrate, a trench which delimits a preliminary active region. A buffer layer may be formed on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C. A sacrificial layer may be formed by replacing the buffer layer. An active region may be exposed by removing the sacrificial layer. A semiconductor liner may be formed on the active region.