Semiconductor Loopback Test Circuit for Stack Memory IO Paths
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Solution Overview
Problem
Existing stack memory systems face challenges in ensuring high-speed data transmission and efficient communication due to the need for reliable loopback testing of physical layers and input/output paths, which are not adequately addressed by current testing methods.
Innovation Solution
A semiconductor device and method that integrates a test control circuit to generate test patterns and signals, along with internal and external IO circuits and storage circuits, to perform loopback operations and check the integrity of write and read operations within the memory system, including micro bumps, TSVs, and memory cells, without requiring external devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a loopback test is performed using external devices to check physical layer connections, then the reliability of connection testing is improved, but the device complexity and testing time increase
Solution Approach 1:
The semiconductor device performs loopback testing using its own internal resources (test control circuit, test pattern generation circuit, and existing IO circuits) without requiring external testing devices. The test control circuit generates test patterns and commands, routes them through the physical layer connections, and compares the returned data to detect connection issues, enabling the device to self-test its own connections.
Solution Approach 2:
The testing circuit utilizes the existing IO circuits (input IO circuit and output IO circuit) that are already part of the semiconductor device's normal operation. These existing circuits are made to serve dual purposes: normal data input/output during operation and test pattern transmission/reception during testing, eliminating the need for dedicated external testing equipment.
2Reliability
If comprehensive testing of IO paths and memory cells is performed, then the reliability of data transmission is improved, but the testing time and productivity are reduced
Solution Approach 1:
The test control circuit generates test patterns and prepares test commands in advance before actual testing begins. The test pattern generation circuit pre-generates multiple test patterns that will be used to comprehensively test both the IO paths and memory cells, allowing the testing process to proceed systematically without delays during execution.
Solution Approach 2:
The testing method combines IO path testing and memory cell testing into a single integrated loopback test process. By routing test patterns through the physical layer connections and into the memory cells, then comparing the returned data, the system simultaneously validates both the connection integrity and memory cell functionality in one unified testing operation.
Data Source
AI summary
A semiconductor device includes a test control circuit generating an external output test pattern based on a test enable signal, an internal output test pattern and an output command signal based on an external input test pattern, and a check result signal based on input read data, an external input/output (IO) circuit generating the external input test pattern by performing a loopback operation based on the external output test pattern, an internal IO circuit generating an internal input test pattern based on the internal output test pattern and an input command signal based on the output command signal and outputting the input read data based on output read data, and a storage circuit storing the internal input test pattern based on the internal input test pattern and the input command signal and extracting the output read data based on the internal input test pattern and the input command signal.