Semiconductor LUN Selection Cycle for Lower Command Overhead
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Solution Overview
Problem
Existing semiconductor systems face increased command overhead and complexity in NAND flash memory systems due to the use of separate command and address interfaces, which degrade performance and complicate internal circuits for parallel operations.
Innovation Solution
A semiconductor system with a first and second semiconductor apparatus that utilizes a LUN selection cycle, enabling a command latch enable signal and an address latch enable signal to selectively receive input and output signals as selection, command, or address signals, reducing unnecessary cycles and simplifying internal circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a separate command address interface (SCA) is used to transmit command address signals and data through different buses, then command overhead is partially reduced, but the internal circuit of the NAND flash memory apparatus becomes complicated to perform parallel operations
Solution Approach 1:
The patent combines the command address interface and data interface into a unified bus structure. The input/output bus simultaneously transmits both command address signals and data, eliminating the need for separate buses. This merging approach reduces the overall system complexity while maintaining efficient command and data transmission capabilities, directly resolving the contradiction between reducing command overhead and avoiding increased internal circuit complexity.
Solution Approach 2:
The unified input/output bus serves multiple functions: it transmits command address signals, transmits data, and supports parallel operations across multiple NAND flash memory apparatuses. This multi-functional design eliminates the need for dedicated separate buses for different signal types, reducing overall system complexity while maintaining the ability to reduce command overhead through efficient signal transmission.
2Speed
If the operating frequency of the NAND flash memory system is increased, then performance is improved, but command overhead increases causing deterioration in memory system performance
Solution Approach 1:
By merging command address and data transmission into a single unified bus, the patent eliminates the need for separate command address cycles that would increase overhead at high frequencies. The unified structure allows more efficient utilization of the bus bandwidth, enabling the system to maintain high operating frequencies without the performance deterioration caused by excessive command overhead.
Data Source
AI summary
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. The first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. The second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.