Semiconductor Device With Magnetic Tunnel Junction And Through Electrode
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Solution Overview
Problem
Conventional embedded semiconductor devices with flash memory face limitations in achieving fast operating speeds due to the slow speed of flash memory devices, necessitating the development of magnetic memory devices that offer high-speed and non-volatile characteristics.
Innovation Solution
A semiconductor device design incorporating a substrate with distinct regions, lower and upper conductive patterns, magnetic tunnel junctions, and through electrodes, along with specific contact and insulation layers, to enhance electrical characteristics and reduce defects, facilitating improved integration and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If flash memory devices are used as main memory elements, then non-volatile characteristics are achieved, but operating speed becomes slow
Solution Approach 1:
The patent changes the fundamental parameter of the memory element from flash memory to magnetic memory (MTJ), which fundamentally alters the operating mechanism from charge-based to magnetization-based, thereby achieving both non-volatility and high-speed operation simultaneously
Solution Approach 2:
The patent replaces the charge-based memory mechanism with a magnetization-based mechanism, substituting the physical principle underlying flash memory operation with magnetic tunneling effects, enabling faster access speeds while maintaining non-volatile characteristics
2Speed
If magnetic memory devices are developed for high speed and non-volatile characteristics, then operating speed improves, but device complexity increases
Solution Approach 1:
The patent divides the magnetic memory device into distinct functional segments: MTJ memory elements for data storage, separate logic circuits for processing, and dedicated interconnect structures, allowing each component to be optimized independently while maintaining overall high performance
Solution Approach 2:
The patent transitions from planar two-dimensional integration to three-dimensional vertical stacking, with MTJ elements stacked above logic circuits, enabling higher integration density without increasing lateral footprint or excessive complexity in any single layer
3Quantity of substance
If high integration is pursued in magnetic memory devices, then memory density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements nested structures where MTJ elements are stacked vertically within compact footprints, and multiple storage layers are nested above logic circuits, achieving high integration density while using standard semiconductor fabrication processes that maintain reasonable precision requirements
Solution Approach 2:
The patent employs universal fabrication processes and standardized interconnect structures that serve multiple functions across different device regions, reducing the variety of precision-critical features and simplifying manufacturing while achieving high integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical characteristics and reduces defects, enabling faster operating speeds and lower power consumption, making it suitable for next-generation memory devices.
Implementation Method 1
a magnetic tunnel junction on the first conductive pattern
Data Source
AI summary
A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.