Semiconductor Identifying Mark on Wiring Metal

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Solution Overview

Problem

In power semiconductor chips, the entire effective region is covered by wiring metal, leaving no space for an identifying mark, which hinders miniaturization as forming a mark in the wiring metal creates an ineffective region where current cannot flow.

Innovation Solution

A semiconductor device with a conductive effective region, a non-conductive ineffective region, wiring metal, a metal section, an identifying mark on the upper surface spaced from the metal section, and an insulating body adjacent to both, allowing the mark to be formed without disrupting current flow, using a manufacturing method that includes forming these regions and structures on the substrate and performing a plating process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If an identifying mark is formed in the wiring metal, then the identifying mark can be provided for traceability, but a section immediately below the identifying mark becomes an ineffective region where no current is allowed to flow, hindering miniaturization

Engineering Contradiction:
Improveidentifying markVSAvoideffective region
Core Design Contradiction:
Loss of informationVSArea of stationary object

Solution Approach 1:

The identifying mark is formed on the upper surface of the wiring metal in the effective region, utilizing the vertical dimension (z-axis) rather than consuming horizontal space. This allows the mark to be positioned above the current-conducting path, maintaining full effective region area while providing identification capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

A metal section is introduced as an intermediary structure between the identifying mark and the wiring metal. The metal section provides a plating surface for forming the identifying mark while being electrically connected to the wiring metal, thus enabling mark formation without disrupting current flow in the effective region.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If the entire effective region is covered by wiring metal to allow large current flow, then current carrying capacity is improved, but there is no room for an identifying mark to be provided

Engineering Contradiction:
Improvecurrent carrying capacityVSAvoididentifying mark
Core Design Contradiction:
PowerVSLoss of information

Solution Approach 1:

The identifying mark is positioned on the upper surface of the wiring metal, utilizing the vertical dimension to provide identification without reducing the horizontal area of the wiring metal. This maintains full current carrying capacity while adding identification functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The identifying mark is nested on top of the wiring metal structure, with the metal section serving as an intermediate layer. This nested arrangement allows the identifying mark to be accommodated within the existing effective region footprint without compromising current flow capacity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the creation of a semiconductor device with an identifying mark suitable for miniaturization by maintaining the effective region's conductivity and preventing the creation of ineffective regions, thus supporting the miniaturization of power semiconductor chips.

Implementation Method 1

performing a plating process on the wiring metal exposed from the insulating body to form, on the effective region, a metal section that is in contact with the insulating body and an identifying mark that is in contact with the insulating body

Methodology Applied
Scientific EffectPlating process: Electroplating

Data Source

PatentUS11398434B2Semiconductor device, and method for manufacturing semiconductor device
Publication Date: 2022.07.26 MITSUBISHI ELECTRIC CORP
  • US11398434B2 patent drawing
  • US11398434B2 patent drawing
  • US11398434B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate, an effective region formed as a conductive section on the semiconductor substrate, an ineffective region formed as a non-conductive section on the semiconductor substrate, a wiring metal formed in the effective region, a metal section provided on an upper surface of the wiring metal and exposed to an outside, an identifying mark provided on the upper surface of the wiring metal and exposed to the outside, the identifying mark being spaced apart from the metal section, and an insulating body provided on the upper surface of the wiring metal and exposed to the outside, the insulating body being adjacent to the metal section and the identifying mark.