Semiconductor Memory Active Area Layout for Uniform Electric Fields
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Solution Overview
Problem
In NAND type flash memories and other semiconductor memories, the compatibility between memory cell miniaturization and reliability is compromised due to the breakage of dummy cells caused by uneven electric fields, leading to functional failures in memory cells sharing word lines with broken dummy cells.
Innovation Solution
The implementation of a closed-loop structured active area layout, achieved through side wall patterning techniques, ensures uniform and narrower active area widths, preventing dummy cell breakage by equalizing electric fields across memory and dummy cells, thereby enhancing reliability and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy area with wider width is set at the endmost portion of the memory cell array to account for exposure margin, then manufacturing precision is improved, but the active area width becomes non-uniform and dummy cells are more susceptible to electric field breakage
Solution Approach 1:
The invention changes the width parameter of active areas from non-uniform (wider at ends) to uniform throughout the array. By making all active areas including dummy areas have the same width, the electric field distribution becomes uniform, preventing the excessive electric field concentration at dummy cells that causes breakage.
Solution Approach 2:
The invention creates equipotential conditions by ensuring uniform active area widths across the entire memory cell array. This uniform geometry results in uniform electric field distribution during write operations, preventing the potential differences and field concentrations that lead to dummy cell breakdown.
2Productivity
If memory cell size is reduced to increase memory capacity, then productivity is improved, but reliability deteriorates due to increased susceptibility to electric field variations
Solution Approach 1:
The invention changes the geometric parameters of active areas to achieve uniform width throughout the array. This parameter optimization allows miniaturization while maintaining uniform electric field distribution, preventing reliability degradation that would otherwise accompany size reduction.
3Manufacturing precision
If conventional lithography with exposure margin is used, then manufacturing precision is improved, but device complexity increases due to non-uniform active area structure
Solution Approach 1:
The invention optimizes the geometric parameters of active areas by setting uniform widths throughout the array. This simplifies the device structure compared to non-uniform designs, while still achieving the necessary manufacturing precision through proper exposure margin consideration in the uniform width design.
Solution Approach 2:
The uniform active area width design serves multiple functions simultaneously: it provides consistent electric field distribution for reliable operation, maintains uniform manufacturing precision across the array, and simplifies the overall device structure by eliminating the need for variable width geometry.
Data Source
AI summary
A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.