Semiconductor Memory Device Asymmetric Drain Source Selection
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Solution Overview
Problem
Current semiconductor memory devices with three-dimensional array structures face challenges in reducing leakage current and maintaining the number of normal memory cells effectively, particularly due to the imbalance in the number of selection transistors and dummy memory cells.
Innovation Solution
The semiconductor memory device incorporates a configuration with more drain selection transistors than source selection transistors and a greater number of drain side dummy memory cells than source side dummy memory cells, forming sub-cell strings that are sequentially stacked and coupled through a pipe transistor to reduce leakage current and maintain the number of normal memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of drain selection transistors is increased to reduce leakage current, then the leakage current is reduced, but the device complexity increases
Solution Approach 1:
The patent applies asymmetry by creating an unbalanced configuration between source and drain sides. Specifically, the drain side has more selection transistors (four drain selection transistors) compared to the source side (three source selection transistors), and the drain side has more dummy memory cells (three drain side dummy memory cells) compared to the source side (two source side dummy memory cells). This asymmetric design allows targeted leakage current reduction at the drain side without unnecessarily increasing complexity on both sides.
Solution Approach 2:
The memory cell string is segmented into functional sections with different numbers of selection transistors and dummy memory cells. The source side has one source selection transistor and two source side dummy memory cells, while the drain side has four drain selection transistors and three drain side dummy memory cells. This segmentation allows each side to be optimized independently for its specific function, reducing overall leakage while managing complexity.
2Reliability
If dummy memory cells are added to reduce leakage current, then the leakage current is reduced, but the number of normal memory cells is reduced
Solution Approach 1:
Dummy memory cells are placed locally at specific positions (source side and drain side of memory cell strings) rather than uniformly throughout the entire memory array. This local placement allows leakage current reduction to be achieved in the critical regions where leakage occurs most, while minimizing the overall impact on the number of normal memory cells. The dummy cells are strategically positioned to affect only the local leakage paths.
3Measurement precision
If more drain selection transistors are used, then the control precision over leakage current is improved, but the device complexity increases
Solution Approach 1:
The patent implements dynamic control of leakage current through multiple drain selection transistors that can be independently controlled. The four drain selection transistors can be selectively activated or deactivated based on operational requirements, allowing dynamic adjustment of leakage current control precision. This dynamic capability enables the system to adapt to different operational states while maintaining manageable complexity through selective activation.
Data Source
AI summary
A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.