3D Semiconductor Memory Device Bit Line Segmentation
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the high cost and complexity of miniaturizing pattern formation, which restricts their capacity and integration density.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a memory cell array with bit lines divided into sections and source line pads, allowing for increased integration without the need for additional dummy bit lines, thereby reducing the device's size and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory device integration is increased through pattern miniaturization, then integration density improves, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory structure to three-dimensional stacked structure. Bit lines are divided into multiple layers (first bit line layer, second bit line layer) stacked vertically, allowing memory cells to be arranged in three dimensions. This dimensional change enables increased integration density without requiring further miniaturization of individual pattern features, thereby avoiding the associated manufacturing complexity and cost increases.
2Quantity of substance
If three-dimensional structure is implemented with stacked gate electrode layers, then capacity and integration increase, but peripheral region size increases
Solution Approach 1:
The patent implements stacked gate electrode layers (first gate electrode layer, second gate electrode layer) vertically over the active region, enabling three-dimensional memory cell arrangement. This vertical stacking increases memory capacity by utilizing the third dimension (height) rather than expanding the peripheral region area horizontally, thus resolving the contradiction between capacity increase and peripheral region size.
Solution Approach 2:
The patent nests multiple functional layers within a compact vertical structure. Gate electrode layers are nested over the active region, bit line layers are nested between gate electrode layers, and insulating layers are nested between conductive layers. This nested arrangement maximizes memory capacity within a small peripheral footprint by efficiently utilizing vertical space.
3Area of stationary object
If bit lines are divided into sections with source line pads, then integration density improves and device size reduces, but electrical connection complexity increases
Solution Approach 1:
The patent divides bit lines into multiple sections (first bit line section, second bit line section) separated by source line pads. This segmentation allows for more flexible routing and reduces the overall device footprint by enabling compact arrangement of memory cells. The segmentation is implemented in a systematic manner that maintains electrical connection simplicity through regular patterning processes.
Solution Approach 2:
The patent resolves connection complexity by transitioning to three-dimensional bit line routing with multiple bit line layers stacked vertically. First bit line layer and second bit line layer provide separate routing paths, allowing source line pads to connect to different bit line sections in different layers. This vertical separation simplifies the electrical connection scheme compared to trying to route all connections in a single plane.
Data Source
AI summary
A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines.