Semiconductor Memory Verification With Simultaneous Bit-Line Precharge
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Solution Overview
Problem
Existing semiconductor memory apparatuses face inefficiencies in current consumption and verification time due to the all bit line precharge method and selective bit line sequential precharge method, which increase current consumption and bit line setup time, degrading operational performance.
Innovation Solution
A semiconductor memory apparatus with a page buffer control circuit that simultaneously precharges bit lines corresponding to multiple verification levels during program and verification operations, reducing current consumption and verification time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the all bit line precharge method is used, then all bit lines are precharged to ensure verification operation, but current consumption increases significantly
Solution Approach 1:
The patent applies local quality by precharging only specific bit lines that are actually needed for the current verification operation, rather than all bit lines uniformly. The page buffer control circuit identifies and selects only the bit lines corresponding to active verification levels, applying precharge voltage locally where required, thus reducing overall current consumption while maintaining verification reliability.
Solution Approach 2:
The patent implements partial action by performing precharge operation on only a subset of bit lines that are required for the current verification task. Instead of applying precharge to all bit lines (excessive action), the system selectively applies it to the necessary portion, optimizing the balance between operational reliability and energy efficiency.
2Use of energy by moving object
If the selective bit line sequential precharge method is used, then current consumption is reduced by precharging only necessary bit lines, but bit line setup time increases
Solution Approach 1:
The patent merges the precharge operations for multiple verification levels into a single simultaneous operation. The page buffer control circuit generates control signals that trigger parallel precharging of all required bit lines at the same time, rather than sequentially. This combines multiple time-separated operations into one concurrent operation, reducing the total setup time while maintaining selective precharge benefits.
Solution Approach 2:
The patent implements preliminary action by precharging the bit lines before the verification operation begins. The page buffer control circuit anticipates the verification needs and prepares the necessary bit lines in advance through simultaneous precharging, ensuring they are ready for immediate verification without delay.
3Use of energy by moving object
If the selective bit line sequential precharge method is used, then current consumption is reduced, but verification time increases due to extended bit line setup time
Solution Approach 1:
The patent merges sequential precharge operations into a single simultaneous precharge operation. The page buffer control circuit coordinates multiple bit line precharges to occur in parallel, combining what would have been time-consuming sequential operations into one efficient concurrent operation, thus maintaining low current consumption while significantly reducing verification time.
Solution Approach 2:
The patent applies dynamics by making the precharge operation adaptive and flexible. The page buffer control circuit dynamically determines which bit lines need precharging based on the current verification requirements, and simultaneously activates them. This dynamic approach allows the system to optimize both current consumption and verification speed by precisely controlling the timing and scope of precharge operations.
Data Source
AI summary
A semiconductor memory apparatus includes a plurality of bit lines, a plurality of page buffers, and a page buffer control circuit. The plurality of page buffers are each coupled with the plurality of bit lines and operate in response to a plurality of page buffer control signals. The page buffer control circuit generates the plurality of page buffer control signals to perform program and verification operations comprising a plurality of loops. The page buffer control circuit uses the plurality of page buffer control signals to simultaneously precharge bit lines coupled with page buffers, among the plurality of page buffers, corresponding to a plurality of verification levels corresponding to each of the plurality of loops.