3D Semiconductor Memory Structure for Leakage-Safe Bit Line Routing
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Solution Overview
Problem
The semiconductor structure with a transistor on capacitor (TOC) configuration is not compatible with peripheral circuits and is prone to leakage, and the manufacturing process is complex and costly.
Innovation Solution
A semiconductor structure comprising a substrate with capacitors arranged in a two-dimensional array, a transistor structure with active pillars and word lines, and a bit line structure above the transistor, where the bit lines are electrically connected to the active pillars, reducing electrical leakage and simplifying the manufacturing process by using a metal material for bit lines and optimizing the dielectric and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor on capacitor (TOC) structure is used, then memory cell functionality is achieved, but compatibility with peripheral circuits is poor and leakage occurs between capacitor and substrate
Solution Approach 1:
The patent transitions from a planar TOC structure to a three-dimensional stacked architecture where capacitors are positioned vertically above transistors. This vertical stacking enables better isolation between capacitive elements and substrate through multiple dielectric layers, while the separated bit line structure above the transistor allows independent routing for peripheral circuit compatibility.
Solution Approach 2:
The bit line structure is segmented into multiple independent conductive layers (first bit line, second bit line, third bit line) that can be independently connected to different active pillars. This segmentation allows flexible routing and connection schemes that improve compatibility with peripheral circuits while maintaining isolation to prevent leakage.
2Reliability
If DRAM manufacturing process is followed, then memory cells are formed, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of transistors and capacitors into a unified stacked structure that can be fabricated using integrated process steps. The capacitive structure is formed in the same semiconductor substrate as the transistor structures, sharing common process steps for substrate preparation, doping, and dielectric deposition, thereby reducing overall manufacturing complexity.
Solution Approach 2:
The stacked structure design allows the same fabrication processes to serve multiple functions: forming both transistor channels and capacitor electrodes, creating isolation regions that serve as both structural support and electrical insulation, and establishing routing layers that function as both interconnect and shielding.
3Device complexity
If conventional bit line configuration is used, then simple structure is maintained, but electrical leakage and resistance increase
Solution Approach 1:
The bit line structure is moved from a planar configuration to a vertical stacked arrangement with multiple conductive layers at different heights. This three-dimensional configuration allows bit lines to be positioned above transistor channels with dielectric layers in between, providing natural electrical isolation that reduces leakage while maintaining low resistance through direct vertical connections to active pillars.
Data Source
AI summary
The present disclosure relates to a semiconductor structure and a forming method thereof. The semiconductor structure includes: a substrate; a capacitive structure, located on a top surface of the substrate and including a plurality of capacitors arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are each parallel to the top surface of the substrate, and the first direction intersects with the second direction; a transistor structure, located above the capacitive structure and including a plurality of active pillars and a plurality of word lines, wherein the active pillar is electrically connected to the capacitor, and the word line extends along the second direction and continuously cover the active pillars arranged at intervals along the second direction; and a bit line structure, located above the transistor structure and including a plurality of bit lines.