Semiconductor Memory Cell Sidewall Spacer Design
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Solution Overview
Problem
In semiconductor technology, achieving a highly negative programming pulse threshold voltage for EEPROMs in high-speed and low operating voltage applications requires additional processing, which increases complexity and costs, making it challenging to meet back-end system requirements.
Innovation Solution
A semiconductor device with a selection gate sidewall spacer formed near the bit line edge, made of the same material as the control gate, which increases the junction breakdown voltage and allows for a higher negative programming pulse threshold voltage without additional processing steps, using a semiconductor substrate with a memory cell comprising a selection transistor and a memory transistor with a floating gate and control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional processing (ion implantation, thermal budget optimization, or high-voltage spacer) is used to increase junction breakdown voltage, then the programming pulse threshold voltage becomes highly negative, but the process complexity and manufacturing costs increase
Solution Approach 1:
The patent merges the formation of the high-voltage spacer with the existing bit line formation process. The bit line material itself is used to form the high-voltage spacer structure, combining two functions (bit line conduction and voltage protection) into a single integrated structure, thereby eliminating additional processing steps while achieving highly negative programming pulse threshold voltage
Solution Approach 2:
The bit line structure is designed to serve multiple functions: it acts as both the data transmission line and the high-voltage protection structure (spacer). This multi-functional design eliminates the need for separate high-voltage spacer processing, reducing manufacturing complexity while maintaining the required junction breakdown voltage for highly negative programming pulse threshold voltage
2Reliability
If additional processing (ion implantation, thermal budget optimization, or high-voltage spacer) is used to increase junction breakdown voltage, then the programming pulse threshold voltage becomes highly negative, but the manufacturing costs increase
Solution Approach 1:
The patent merges the formation of the high-voltage spacer with the existing bit line formation process. The bit line material itself is used to form the high-voltage spacer structure, combining two functions (bit line conduction and voltage protection) into a single integrated structure, thereby eliminating additional processing steps while achieving highly negative programming pulse threshold voltage
Solution Approach 2:
The bit line structure serves itself by forming the high-voltage spacer from its own material. The existing bit line deposition and patterning processes automatically create the protective spacer structure, requiring no additional materials or processing steps, thereby reducing manufacturing costs while achieving the required junction breakdown voltage
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a memory cell disposed on the semiconductor substrate. The memory cell includes a selection transistor and a memory transistor. The selection transistor includes a selection gate, a first source, and a first drain. The memory transistor includes a floating gate, a control gate, a second source, a second drain, and a first insulating layer disposed between the floating gate and the control gate. The semiconductor device further includes a selection gate sidewall spacer disposed near an edge of a bit line of the selection gate of the selection transistor. The selection gate sidewall spacer is separated from the selection gate by a second insulating layer. The selection gate sidewall spacer and the control gate are formed of a first material.