3D Semiconductor Memory With Single Crystalline Silicon Channel
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and performance while maintaining low power consumption and nonvolatile data storage.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a cell string structure featuring conductive pillars, channel layers made of single crystalline silicon, and a ferroelectric layer, which are stacked to improve electrical characteristics and enable efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor memory structures are used, then manufacturing process is simpler, but integration density and electrical performance are insufficient
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertically stacked structures. Multiple memory cells are stacked in the vertical direction, with channel layers arranged at different heights, enabling significantly higher integration density while maintaining manufacturability through systematic layering of electrodes, ferroelectric layers, and channel layers.
Solution Approach 2:
The patent implements a nested structure where memory cells are contained within cell strings, which are vertically stacked. Each memory cell comprises nested layers including channel layers, ferroelectric layers, and electrodes, with conductive pillars penetrating through multiple layers. This nested arrangement maximizes space utilization and achieves high integration density.
2Reliability
If amorphous silicon channel layer is used, then manufacturing is easier, but carrier mobility is insufficient for high performance
Solution Approach 1:
The patent changes the crystalline state parameter of the channel layer material from amorphous to single crystalline silicon. This parameter change dramatically improves carrier mobility and electrical performance. The single crystalline structure is achieved through controlled epitaxial growth or selective laser annealing processes that maintain crystal orientation and reduce defects.
Solution Approach 2:
The patent employs composite material structures where single crystalline silicon channel layers are combined with ferroelectric materials (such as hafnium oxide) and various electrode materials. This composite approach leverages the high carrier mobility of single crystalline silicon while incorporating the nonvolatile storage properties of ferroelectric materials, achieving both high performance and nonvolatility.
3Productivity
If vertically stacked memory cells are implemented, then integration density improves, but leakage current between cells increases
Solution Approach 1:
The patent segments the vertically stacked structure into isolated memory cells by introducing insulating layers between adjacent channel layers and cell strings. These insulating layers act as barriers that prevent electrical leakage between vertically adjacent cells and laterally adjacent cell strings, enabling high integration density without compromising electrical isolation.
Solution Approach 2:
The patent introduces insulating materials as intermediary layers between conductive elements. These insulating layers are positioned between channel layers, around conductive pillars, and between cell strings to provide electrical isolation. The intermediaries prevent direct electrical contact between adjacent cells, eliminating leakage current paths while maintaining the compact vertical architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves enhanced carrier mobility and reduced leakage current, leading to improved electrical characteristics and nonvolatile data storage capabilities.
Implementation Method 1
a ferroelectric layer on the channel layer
Implementation Method 2
The channel layer may comprise single crystalline silicon
Data Source
AI summary
A semiconductor memory device includes a cell string and a first conductive pillar and a second conductive pillar connected to the cell string. The cell string includes plural memory cells, which are stacked on a substrate to be spaced apart from each other. The first conductive pillar is spaced apart from the second conductive pillar in a first direction. Each of the memory cells includes a channel layer that extends from the first conductive pillar to the second conductive pillar in the first direction, a ferroelectric layer on the channel layer, and an electrode on the ferroelectric layer. The channel layer comprises single crystalline silicon.