Semiconductor Memory Contact Plug Oblique Arrangement
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Solution Overview
Problem
The miniaturization of memory cell arrays in semiconductor memory devices leads to challenges such as increased risk of contact shorts, decreased breakdown voltage, and increased contact resistance, which are difficult to address with traditional staggered contact arrangements without expanding chip area.
Innovation Solution
A semiconductor memory device with a contact region that includes alternating patterns of three-contact and two-contact oblique arrangements, where contact plugs are arranged on device regions in a non-parallel straight line configuration, ensuring a consistent pitch and distance to maintain electrical integrity and reduce chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If contact plugs are miniaturized to reduce chip area, then chip area is reduced, but contact resistance increases and reliability decreases
Solution Approach 1:
The patent transitions from a conventional linear contact arrangement to a two-dimensional staggered grid pattern. Contact plugs are arranged in alternating rows with different spacing, creating a denser packing that reduces chip area while maintaining adequate separation distances to prevent shorts and maintain reliability.
Solution Approach 2:
The contact plugs are arranged in an asymmetric staggered pattern where adjacent rows have different pitch values. This asymmetric arrangement optimizes space utilization by creating a more efficient packing density compared to uniform spacing, thereby reducing chip area while maintaining electrical integrity.
2Quantity of substance
If distance between contacts is reduced to increase density, then contact density increases, but risk of contact shorts increases
Solution Approach 1:
The contact array is segmented into multiple rows with alternating pitch values. This segmentation allows different regions to have optimized spacing - tighter in some rows for density, while maintaining larger spacing in adjacent rows to prevent shorts, thereby resolving the contradiction between density and short risk.
Solution Approach 2:
The staggered arrangement creates intermediate spacing zones between contact plugs in adjacent rows. These intermediate zones act as buffer regions that provide additional clearance and reduce the probability of shorts while maintaining high overall contact density.
3Reliability
If multiple-contact staggered arrangement is used to prevent contact shorts, then reliability improves, but chip area increases
Solution Approach 1:
The patent merges multiple contact plugs into a compact staggered grid structure where contacts from different rows interleave. This merging achieves high contact density and reliability within a minimized footprint by combining the benefits of multiple-contact spacing with efficient space utilization.
Solution Approach 2:
The patent employs variable pitch parameters across different rows of contact plugs. By changing the spacing parameter selectively in alternating rows, the design achieves optimal balance between preventing contact shorts (requiring larger spacing) and minimizing chip area (requiring smaller spacing).
Data Source
AI summary
In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.