Semiconductor Memory Device Counter Implanted Well Power Reduction
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Solution Overview
Problem
In semiconductor memory devices with three-dimensional structures, increasing integration leads to higher power consumption, and existing manufacturing methods struggle to efficiently manage this, particularly in the configuration and manufacture of peripheral circuits.
Innovation Solution
The implementation of a semiconductor memory device with a counter implanted well structure, where a P-type counter implanted well is formed along the bottom surface of an element isolation insulating film, offset from its ends, to increase resistance and reduce power consumption, while also allowing for simultaneous doping of impurities to form transistor regions, thereby enhancing electrical connectivity and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure with stacked memory cell layers is implemented to increase integration, then memory capacity is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by creating a counter implanted well with opposite conductivity type specifically in the peripheral circuit region, while maintaining the original well structure in memory cell regions. This localized modification allows power consumption reduction in peripheral circuits without affecting memory cell operation, thereby addressing the power consumption increase issue while preserving high memory capacity.
Solution Approach 2:
The patent changes the conductivity type parameter by forming a counter implanted well with conductivity type opposite to the original well in the peripheral circuit region. This parameter change creates electrical characteristics that reduce power consumption in peripheral circuits while maintaining the three-dimensional stacked structure for high memory capacity.
2Quantity of substance
If peripheral circuits are configured in three-dimensional structures, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the substrate into memory cell regions and peripheral circuit regions, applying different well structures to each. The counter implanted well is formed only in peripheral circuit regions, separating the manufacturing complexity from memory cell production while maintaining high integration through the three-dimensional stacked structure.
Solution Approach 2:
The counter implanted well is formed preliminarily in the peripheral circuit region before final device assembly. This preliminary action simplifies subsequent manufacturing steps by pre-establishing the electrical characteristics needed for low power consumption in peripheral circuits, reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively manages power consumption by maintaining reliable electrical connections and increasing resistance, while reducing manufacturing complexity and costs, thus addressing the challenges of increased integration in three-dimensional memory devices.
Implementation Method 1
an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate
Implementation Method 2
forming a first well by doping an impurity having a first conductivity type in the semiconductor substrate
Implementation Method 3
forming a second well by overlappingly doping an impurity having a second conductivity type in the first well
Implementation Method 4
a contact line electrically connected to the first well
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.