Semiconductor Memory Device with Local Impurity Control
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Solution Overview
Problem
High integration and high-speed semiconductor memory devices face challenges in connecting semiconductor layers to gate electrodes efficiently, particularly with increasing aspect ratios, which complicates the removal of gate insulating films and affects read and erase operations due to issues like gate-induced drain leakage and resistance control.
Innovation Solution
A semiconductor memory device structure where the semiconductor layer 140 is a P-type layer, connected to the outer peripheral surface of the semiconductor layer 120, allowing for efficient hole supply during erase operations and reducing resistance between the semiconductor layer 120 and the conductive layer 150, with specific impurity concentrations to manage channel region impurities effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating film is removed to connect the semiconductor layer to the gate electrode, then the connection is achieved, but the aspect ratio increases and manufacturing complexity increases
Solution Approach 1:
The gate insulating film is selectively removed (extracted) from the contact region to establish direct electrical connection between the semiconductor layer and gate electrode. This extraction approach achieves reliable connection while controlling the removal process to avoid excessive aspect ratio increases and manufacturing complexity
Solution Approach 2:
The gate insulating film is removed only in specific local regions where connection is needed, while maintaining the film in other regions. This local quality approach ensures connection reliability at contact points without increasing overall device complexity or aspect ratio
2Reliability
If the semiconductor layer is connected to the gate electrode, then electrical connection is achieved, but gate-induced drain leakage occurs affecting read and erase operations
Solution Approach 1:
The semiconductor layer is configured with different impurity concentrations in different regions: a first concentration in the channel region and a second concentration at the connection region. This local quality differentiation suppresses gate-induced drain leakage at the connection interface while maintaining proper electrical connection
Solution Approach 2:
The impurity concentration parameter is changed between different regions of the semiconductor layer. By adjusting the impurity concentration at the connection region, the patent achieves reliable electrical connection while minimizing gate-induced drain leakage effects on read and erase operations
3Productivity
If the resistance between semiconductor layer and conductive layer is reduced, then high-speed operations are achieved, but impurity distribution control becomes more challenging
Solution Approach 1:
The semiconductor layer has different impurity concentrations in different regions: the channel region maintains one concentration for proper transistor operation, while the connection region has a different concentration optimized for low resistance. This local quality approach achieves high-speed operations without compromising overall manufacturing precision
Solution Approach 2:
The semiconductor layer is segmented into regions with different impurity concentrations. This segmentation allows independent optimization of each region: the channel region for transistor performance and the connection region for low resistance, thereby achieving high-speed operations while maintaining manufacturing precision through controlled impurity distribution
Data Source
AI summary
A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.