Semiconductor Memory Device Dynamic Voltage Control
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Solution Overview
Problem
Non-volatile memory devices, such as NAND flash memory, face instability issues due to the high voltage required for FN tunneling, which affects the program operation of memory cells and leads to undesirable data storage.
Innovation Solution
A semiconductor memory device and method that control the FN tunneling speed by self-boosting the cell channel and controlling the discharge time of the cell channel for memory cells programming data '0', using a voltage supply circuit to provide specific voltages to coupling circuits and page buffers for a soft program operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage (15 V or higher) is applied to control gates for FN tunneling, then program operation is enabled, but memory cell stability deteriorates
Solution Approach 1:
The patent applies dynamics by making the control gate voltage time-dependent rather than constant. The voltage starts at a first level during initial tunneling, then transitions to a second level during the tunneling process, and finally to a third level after tunneling. This dynamic voltage adjustment allows the system to maintain program operation capability while improving memory cell stability through reduced voltage stress during critical tunneling phases.
Solution Approach 2:
The patent changes the voltage parameter dynamically during the program operation. By transitioning control gate voltage from a first voltage level to a second voltage level and then to a third voltage level, the system optimizes the FN tunneling process. This parameter change allows achieving program operation with reduced voltage stress, thereby improving memory cell stability and reducing threshold voltage distribution issues.
2Productivity
If high voltage is applied for limited time during FN tunneling, then program operation is achieved, but threshold voltage distribution becomes unstable
Solution Approach 1:
The patent uses dynamic voltage adjustment to control the tunneling process in three distinct phases. The control gate voltage transitions from a first level (for initial tunneling) to a second level (during active tunneling) and finally to a third level (after tunneling). This dynamic approach ensures uniform threshold voltage distribution by preventing excessive voltage stress while maintaining adequate program operation speed.
Solution Approach 2:
The patent implements periodic voltage adjustment during the program operation. The control gate voltage is changed at specific time intervals: initially at a first level, then switched to a second level during tunneling, and finally to a third level after tunneling completes. This periodic voltage change pattern ensures consistent threshold voltage distribution across all memory cells while maintaining efficient program operation.
3Reliability
If cell channel discharge time is controlled for soft program operation, then program stability is improved, but operation time increases
Solution Approach 1:
The patent applies dynamic voltage control to the cell channel discharge process. The discharge time is not fixed but is dynamically adjusted based on the tunneling progress and cell state. By transitioning control gate voltage through multiple levels, the system achieves stable program operation with optimized discharge time, balancing reliability and operation duration.
Solution Approach 2:
The patent changes the discharge time parameter dynamically during the program operation. By adjusting the control gate voltage from a first level to a second level and then to a third level, the system optimizes the discharge time for each phase. This parameter adjustment ensures stable program operation while minimizing unnecessary time extension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the program operation by controlling the FN tunneling speed and discharge time, reducing the risk of excessive threshold voltage changes in memory cells, allowing for a slow and fine program operation without additional circuits or algorithms.
Implementation Method 1
a program operation on memory cells is performed using an FN tunneling method. The FN tunneling method is performed by providing a voltage of 15 V or higher to control gates while the cell channel of the memory cells is set to 0 V, thereby allowing electrons to move from the cell channel to floating gates.
Data Source
AI summary
A semiconductor memory device is operated by, inter alia: precharging a bit line, providing a first voltage to a coupling circuit for coupling the bit lines and cell strings of a plurality of memory cells, providing a program voltage to a selected word line coupled to a memory cell on which a program operation will be performed among the plurality of memory cells, providing a pass voltage to unselected word lines, providing a second voltage lower than the first voltage to the coupling circuit, discharging the bit line by loading program data, and providing a third voltage lower than the second voltage to the coupling circuit.