3D Stacked Semiconductor Memory Error Correction via Syndrome Tracking
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Solution Overview
Problem
The increasing demand for large capacity and small footprint semiconductor memory devices with 3D stacked structures poses challenges in efficiently detecting and correcting errors in memory cells, particularly due to the reduced size and integration of memory chips, which existing technologies struggle to address effectively.
Innovation Solution
A semiconductor memory device is designed with a buffer die, multiple memory dies stacked via through silicon vias (TSVs), incorporating a memory cell array, an error correction code (ECC) engine, an error information register, and a control logic circuit that performs read-modify-write operations to detect and correct errors, determining error attributes based on syndrome changes and storing fail addresses and corrected data for soft post-package repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are reduced in size and integrated in 3D stacked structure to increase capacity, then memory capacity and integration are improved, but error detection and correction capability deteriorates
Solution Approach 1:
The memory device is divided into multiple memory dies stacked in 3D structure, with each die containing independent memory cell arrays. ECC engines are distributed across different dies to perform localized error correction, enabling reliable operation despite reduced individual die size and increased integration density.
Solution Approach 2:
Through silicon vias (TSVs) are introduced as intermediary structures to connect memory dies vertically, enabling data and control signal transmission between stacked layers. This intermediary connection method allows high-density 3D integration while maintaining electrical connectivity for error correction operations across multiple dies.
2Quantity of substance
If 3D stacked structure with multiple memory dies is used to increase integration, then memory density is improved, but error management complexity increases
Solution Approach 1:
Error correction codes are pre-calculated and stored in redundancy memory locations within each memory die. When errors are detected during read operations, the pre-prepared corrected data is immediately retrieved and written back to the defective location, eliminating the need for complex real-time error management across the 3D stacked structure.
Solution Approach 2:
Each memory die performs self-diagnosis and self-correction of errors through integrated ECC engines and read-modify-write operations. The system automatically detects errors, retrieves corrected data from redundancy locations, and repairs defective cells without external intervention, simplifying error management in densely integrated 3D structures.
Data Source
AI summary
A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.