Semiconductor Memory Device Edge Gate Insulator Thickness
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Solution Overview
Problem
Low voltage transistors with narrow widths in semiconductor devices exhibit high leakage current characteristics due to reduced impurity concentration at the edges of the active region, leading to parasitic transistor formation and deteriorated leakage current characteristics.
Innovation Solution
A semiconductor device manufacturing method involving the formation of a thicker first gate insulating layer at the edges and a thinner second gate insulating layer at the center of low voltage transistors, which increases the threshold voltage at the edges, thereby reducing leakage current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurities for controlling threshold voltage are implanted into the active region to improve leakage current characteristics, then leakage current characteristics are improved, but impurity concentration at the edges of the active region is reduced during subsequent processes
Solution Approach 1:
The patent applies local quality by forming a thicker gate insulating layer specifically at the edge regions of the active region where impurity concentration is reduced, while maintaining a thinner gate insulating layer at the center region. This localized structural adjustment compensates for the non-uniform impurity distribution and prevents parasitic transistor formation at the edges without affecting the overall device performance.
2Reliability
If a thicker gate insulating layer is formed at the edges of the active region to prevent parasitic transistor formation, then leakage current characteristics are improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the thicker gate insulating layer at the edge regions before forming the gate electrode and other subsequent structures. This preliminary structural adjustment ensures that the threshold voltage is properly controlled at the edges from the beginning, preventing parasitic transistor formation in advance and eliminating the need for additional corrective processes later.
3Reliability
If additional impurity implantation is performed through a mask to compensate for edge region impurity loss, then leakage current characteristics can be maintained, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the gate insulating layer thickness parameter rather than adding additional impurity implantation steps. By changing the physical dimension (thickness) of the gate insulating layer at the edge regions, the patent achieves compensation for impurity loss through a geometric parameter adjustment, which is simpler and more controllable than additional chemical implantation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current characteristics by increasing the threshold voltage at the edges of low voltage transistors, improving the operational stability of low voltage transistors with narrow widths.
Implementation Method 1
a first gate insulating layer thicker than the second gate insulating layer, wherein the first gate insulating layer is formed at edges of the second driving transistor region, and a second gate insulating layer formed at a center of the second driving transistor region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a first driving transistor region having a first driving transistor disposed therein and a second driving transistor region having a second driving transistor disposed therein, wherein the second driving transistor is driven at a lower voltage than the first driving transistor, a first gate insulating layer formed at edges of the second driving transistor region, and a second gate insulating layer formed at a center of the second driving transistor region, wherein the first gate insulating layer is thicker than the second gate insulating layer.