Semiconductor Memory Repair Controller for Edge Word-Line Defects
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Solution Overview
Problem
As the size of memory cell arrays in volatile memory devices increases, memory cells connected to edge word-lines adjacent to the edges of sub-array blocks are more susceptible to defects, leading to performance issues.
Innovation Solution
A semiconductor memory device with a repair controller that includes fuse boxes to activate redundancy word-lines, replacing defective and edge word-lines based on access and reset addresses, thereby forcibly repairing these vulnerable lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory cell arrays is increased, then the storage capacity is improved, but the susceptibility of edge word-lines to defects increases
Solution Approach 1:
The patent pre-loads defective addresses and reset addresses into fuse boxes before normal operation. When an edge word-line defect occurs, the repair controller can immediately activate the corresponding redundancy word-line by comparing the current access address with the pre-stored addresses, enabling rapid defect repair without increasing physical area.
Solution Approach 2:
The patent creates redundancy word-lines as copies of normal word-lines. These redundancy word-lines serve as backup replacements that can be activated when edge word-lines become defective, allowing the system to maintain functionality without requiring additional physical memory cells beyond the redundancy structures.
2Reliability
If redundancy word-lines are activated to replace defective edge word-lines, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The fuse boxes serve multiple functions: they store both defective addresses and reset addresses, and they provide pre-computed redundancy word-line addresses. This multi-functionality reduces the need for separate storage structures and complex address generation logic, simplifying the overall repair controller design while maintaining reliable defect repair capability.
Solution Approach 2:
The repair controller automatically performs address comparison and redundancy word-line activation without external intervention. The fuse boxes self-manage the storage and retrieval of repair addresses, and the repair controller autonomously determines when to activate redundancy word-lines based on address matching, reducing the need for additional control logic.
3Ease of repair
If fuse boxes are used to store defective addresses, then the ease of repair is improved, but the occupied area increases
Solution Approach 1:
The patent merges the storage of defective addresses and reset addresses into the same fuse box structure. By combining these two address storage functions into a single fuse box, the patent reduces the total area required compared to having separate storage structures, while still providing comprehensive defect repair capability for both defective word-lines and edge word-lines.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.