Semiconductor Memory Fabrication Single Mask Set
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost of mask sets required for producing semiconductor memory devices of different capacities, such as 3D multi-layer NAND or OTP memory, necessitates the development of a method to fabricate memory chips with varying capacities using a single mask or reticle set.
Innovation Solution
A semiconductor memory manufacturing method involving the fabrication of basic memory modules on a wafer with IO circuit interfaces, dicing to separate memory chips, and interconnecting modules via controllable lines, allowing for the production of memory chips of different capacities using a single mask set by adjusting the number and position of modules and enabling/disabling interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different mask sets are used for each memory capacity, then manufacturing precision is maintained, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies universality by designing a single mask set that can be used to manufacture multiple memory capacities (4GB, 8GB, 16GB, 32GB, 64GB) through different configurations of basic memory modules. The basic memory module design allows the same mask pattern to be replicated and interconnected in various arrangements to achieve different total capacities, eliminating the need for separate mask sets for each capacity level.
Solution Approach 2:
The patent segments the memory chip into multiple basic memory modules (e.g., four 1GB modules to form 4GB, eight 1GB modules to form 8GB). Each basic module is fabricated using the same mask set, and the final memory capacity is achieved by interconnecting these segmented modules in different configurations. This segmentation allows a single mask set to produce multiple capacity variants.
2Adaptability or versatility
If multiple mask sets are developed for different capacities, then product versatility is achieved, but development time and complexity increase
Solution Approach 1:
The patent creates a universal basic memory module design that can be configured to produce multiple memory capacities. The same mask set and basic module design serve multiple functions by varying the number and interconnection of modules, thereby achieving product versatility without increasing mask set complexity or management burden.
Solution Approach 2:
The patent introduces dynamic configurability at the module interconnection level. While the basic memory modules are fabricated identically using the same mask set, the interconnection patterns between modules can be dynamically configured during packaging or testing to achieve different capacity variants. This dynamic approach allows versatility without requiring different mask sets for each configuration.
3Speed
If basic memory modules are interconnected via interconnection lines, then transmission speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory architecture into discrete basic memory modules with standardized interconnection interfaces. Each module maintains its own internal high-speed connections, and the inter-module interconnection lines are designed with standardized routing patterns that reduce alignment complexity. This segmentation allows high-speed performance within modules while simplifying the precision requirements for inter-module connections.
Data Source
AI summary
A semiconductor memory fabrication method and the semiconductor memory are involved in semiconductors production and fabrication processes. The semiconductor memory manufacturing method of the present invention includes the following steps: 1) Using a semiconductor integrated circuit manufacturing process, a basic memory module array being fabricated on a wafer where the basic memory modules have IO circuit interfaces; 2) Dicing the wafer to obtain memory chips; 3) Packaging the separated memory chip. In step 1), the IO circuit interfaces of the basic memory modules adjacent in the orthogonal directions are connected by interconnection lines; and according to the predetermined memory capacity, step 2) is to determine the number of basic memory modules contained in the chip and the position of the edge line of the memory chip so that the interconnections across the edge line are cut off so to separate the entire memory chip from the wafer by dicing along the edge line of the memory chip. Using the technique of the present invention, memory chips of multiple different capacities can be produced with solely one set of masks or reticles, which greatly reduces the manufacture cost.