Semiconductor Memory Device Gate Structure Dopant Neutralization
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Solution Overview
Problem
The integration of transistors in semiconductor memory devices often results in neutralization of N-type and P-type dopants during thermal processes, preventing the achievement of dual work function gates, which limits the performance and flexibility of memory devices.
Innovation Solution
A method combining a triple gate dielectric layer process and a dual work function gate process, where ion implantation is performed separately for the cell and periphery regions to avoid dopant neutralization, allowing for the formation of N-type and P-type conductive gates, thereby enhancing device performance and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If N-type gate electrodes and P-type gate electrodes are respectively formed on the periphery region by using a lithography process and an ion implantation process, then the dual work function gate structure can be achieved, but a subsequent thermal process may cause neutralization of N-type dopant and P-type dopant, so that the structure and effect of dual work function gate cannot be achieved
Solution Approach 1:
The patent applies preliminary action by performing ion implantation to form N-type and P-type gate electrodes in the periphery region before any thermal processes that could cause dopant neutralization. The gate electrodes are formed with appropriate dopant types and concentrations in advance, and subsequent processes are designed to avoid thermal treatment that would neutralize the dopants, thereby preserving the dual work function gate structure.
Solution Approach 2:
The patent applies local quality by differentiating the gate electrode structures in the periphery region from those in the cell region. The periphery region gate electrodes are specifically designed with N-type or P-type dopant characteristics through selective ion implantation, while the cell region maintains different gate structures. This local differentiation allows the periphery region to achieve dual work function gates without affecting the overall device performance.
2Productivity
If elements on cell region and periphery region are integrated in a single chip to reduce cost and simplify steps, then manufacturing efficiency is improved, but the phenomenon of neutralization of N/P-type dopants caused by thermal process occurs
Solution Approach 1:
The patent applies segmentation by dividing the chip into distinct cell region and periphery region with different gate structures. The periphery region is further segmented into areas with N-type gate electrodes and areas with P-type gate electrodes. This segmentation allows each region to be optimized independently, enabling the integration of multiple elements on a single chip while preventing dopant neutralization through region-specific process control.
Solution Approach 2:
The patent applies parameter changes by controlling the dopant type, concentration, and distribution parameters through selective ion implantation processes. By adjusting these parameters in different regions and at different stages of manufacturing, the patent achieves both high manufacturing efficiency through integration and prevents dopant neutralization by maintaining appropriate dopant characteristics throughout the thermal processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor memory devices by preventing dopant neutralization and allowing for flexible configuration, enabling better integration of elements on a single chip.
Implementation Method 1
A first ion implantation process is performed, so that conductive types of the second floating gate and the second control gate are changed to a first conductive type. A second ion implantation process is performed, so that conductive types of the third floating gate and the third control gate are changed to a second conductive type.
Data Source
AI summary
A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.