Semiconductor Memory Gate Electrode Impurity Diffusion Control

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Solution Overview

Problem

The formation of ONO films at high temperatures in semiconductor device manufacturing diffuses impurities in the peripheral circuit region, leading to variations in threshold voltage of MISFETs and affecting the performance of nonvolatile memory devices.

Innovation Solution

A method involving the formation of a control gate electrode and insulation films, followed by etching back the second conductive film to create a memory gate electrode, which helps in preventing impurity diffusion and maintaining impurity concentration distribution, thereby improving the semiconductor device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If ONO film is formed at high temperature, then the memory cell structure is successfully formed, but impurity diffusion occurs in the peripheral circuit region causing threshold voltage variation

Engineering Contradiction:
Improvememory cell structure formationVSAvoidthreshold voltage stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the semiconductor device into two distinct regions: a first region (memory cell region) where high-temperature processing is performed to form the ONO film and memory gate electrode, and a second region (peripheral circuit region) where the semiconductor region is formed later at lower temperatures. This spatial segmentation allows the memory cell region to undergo necessary high-temperature processing while protecting the peripheral circuit region from impurity diffusion, thus resolving the contradiction between manufacturing precision and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different processing conditions to different regions: the memory cell region receives high-temperature ONO film formation and etch back processing to achieve precise memory structure formation, while the peripheral circuit region undergoes lower-temperature processing to maintain impurity concentration distribution and threshold voltage stability. This local quality approach allows each region to have optimal processing conditions for its specific function.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of semiconductor devices by maintaining the impurity concentration distribution and preventing threshold voltage variations, leading to improved reliability and efficiency of nonvolatile memory operations.

Implementation Method 1

an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film

Methodology Applied
Scientific EffectEtching:

Implementation Method 4

the impurity doped into the well in the peripheral circuit region is diffused at a high temperature during the formation of the ONO film

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9324726B2Method for manufacturing a semiconductor device
Publication Date: 2016.04.26 RENESAS ELECTRONICS CORP
  • US9324726B2 patent drawing
  • US9324726B2 patent drawing
  • US9324726B2 patent drawing

AI summary

The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.