Semiconductor Memory Device With Varying Ge Concentration Layer
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Solution Overview
Problem
The existing three-dimensionally stacked semiconductor memory devices face challenges in increasing memory density without increasing lithography steps, particularly due to the need for insulating film removal using diluted hydrofluoric acid and the complexity of interconnection layers that affect chip occupation ratio and operating speed.
Innovation Solution
A semiconductor memory device structure where a single-crystal semiconductor layer with varying Ge concentration is formed above a memory cell array, allowing the control circuit to be positioned above the memory cell array, reducing the need for bottom insulating film removal and optimizing interconnection layers for reduced chip area and improved operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the control circuit is formed below the memory cell array, then the chip occupation ratio is reduced, but the bit line interconnection length increases and deep contacts are required
Solution Approach 1:
The patent inverts the conventional arrangement by forming the control circuit above the memory cell array instead of below it. This inversion eliminates the need for long bit line interconnections and deep contacts, as the control circuit can directly access the memory cell array through shorter vertical interconnections, thereby resolving the contradiction between chip occupation ratio and interconnection length
Solution Approach 2:
The patent utilizes the vertical dimension by stacking the control circuit above the memory cell array in the third dimension. This three-dimensional arrangement allows the control circuit to be positioned closer to the memory cell array without increasing planar chip area, thus reducing interconnection length while maintaining efficient chip space utilization
2Reliability
If the insulating film is removed from the bottom of the memory hole using diluted hydrofluoric acid, then the polysilicon film connection is improved, but the memory film configuration flexibility is reduced
Solution Approach 1:
The patent extracts and eliminates the requirement for bottom insulating film removal by adopting a U-shaped silicon pillar structure. This structure naturally provides polysilicon-to-polysilicon contact without requiring hydrofluoric acid treatment, thereby maintaining reliable electrical connection while freeing the memory film configuration from processing constraints and enabling greater design flexibility
3Ease of manufacture
If deep contacts are formed in the memory cell array periphery, then the control circuit can be connected below the array, but the region size and chip area increase
Solution Approach 1:
The patent inverts the connection approach by forming the control circuit above the memory cell array rather than below it. This eliminates the need for deep contacts in the periphery region, as the control circuit can be directly connected through shorter vertical interconnections, thereby reducing the required periphery region size and simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory density without increasing lithography steps, reduces chip area by eliminating the need for deep contacts, and improves operating speed by shortening interconnections, while allowing for flexible control circuit design and high breakdown voltage characteristics.
Implementation Method 1
a single-crystal semiconductor layer 109, in which a Ge concentration in a lower portion of the single-crystal semiconductor layer 109 on the memory cell array portion is higher than a Ge concentration in an upper portion
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.