3D Semiconductor Memory Device With Nested Pass Gate
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and capacity, particularly in the development of three-dimensional (3D) semiconductor memory devices.
Innovation Solution
The semiconductor memory device includes a transistor, a molded insulating structure with overlapping and sideways extending areas, a pass gate in the sideways area, an active pillar penetrating the pass gate, a pass gate insulating layer, and a cell array structure with memory cells arranged in three dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions to achieve high capacity, then the storage capacity increases, but the device complexity increases
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to three-dimensional (3D) stacking, where memory cells are arranged vertically across multiple layers. This dimensional change enables significantly higher storage capacity by utilizing the vertical space above the substrate, allowing multiple bit lines and word lines to be stacked in different heights without increasing the footprint area.
Solution Approach 2:
The memory device is divided into multiple functional layers and regions, including first and second bit line regions, first and second word line regions, and multiple memory cell layers. This segmentation allows independent optimization of each region and simplifies the manufacturing process by enabling modular fabrication of complex 3D structures.
2Productivity
If the molded insulating structure extends sideways to accommodate pass gates, then the integration density improves, but the manufacturing precision requirements increase
Solution Approach 1:
The molded insulating structure is formed with a first area that overlaps the transistor and a second area that extends sideways, creating a nested spatial arrangement. The pass gate is positioned within the second area, and the active pillar penetrates through the pass gate, forming a nested configuration where multiple components occupy overlapping or intersecting spatial regions. This nesting enables higher integration density by efficiently utilizing three-dimensional space.
3Reliability
If multiple conductive connection structures are disposed in the first area, then the electrical connectivity improves, but the area occupied by connection structures increases
Solution Approach 1:
Multiple first conductive connection structures are disposed within the first area of the molded insulating structure at different vertical heights or positions, enabling improved electrical connectivity between the transistor and various memory cell components. By utilizing vertical stacking and three-dimensional positioning, the patent achieves enhanced connectivity without proportionally increasing the planar area occupied by these connection structures.
Data Source
AI summary
Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a transistor, a cell array structure, a molded insulating structure including a first area disposed between the transistor and the cell array structure and overlapping with the transistor and a second area extending sideways from the first area, a pass gate disposed in the second area of the molded insulating structure, an active pillar penetrating the pass gate, and a pass gate insulating layer disposed between the active pillar and the pass gate.