Semiconductor Memory Pad Redirection for Wire Length Reduction

Solution Overview

Problem

The increasing length of backend interconnection wires in semiconductor memory leads to higher power consumption and reduced signal integrity, necessitating a reduction in wire length to improve performance.

Innovation Solution

The semiconductor memory design incorporates first and second pads arranged in parallel directions with interconnection wires extending in opposite directions, forming a redistribution layer that reduces the overall length of interconnection wires, thereby minimizing power consumption and enhancing signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the backend interconnection wires are extended to connect inner pads to outer pads, then the pads can be redistributed to appropriate positions, but the wire length increases leading to higher power consumption and reduced signal integrity

Engineering Contradiction:

Improvepad redistribution capabilityVSAvoidpower consumption of interconnection wires

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces a third dimension (vertical stacking) to the traditional planar pad arrangement. By forming upper and lower pads at different vertical levels and connecting them through vertical interconnection wires, the design redistributes pads in three-dimensional space rather than extending wires horizontally across the backend, thus reducing wire length while maintaining redistribution capability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The pad arrangement is segmented into multiple groups (upper pads and lower pads) positioned at different vertical levels. This segmentation allows independent optimization of wire connections for each group, enabling shorter interconnection paths compared to a single-layer arrangement where all pads would require long horizontal connections

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the backend interconnection wires are extended to connect inner pads to outer pads, then the pads can be redistributed to appropriate positions, but the signal integrity is reduced due to longer wire length

Engineering Contradiction:

Improvepad redistribution capabilityVSAvoidsignal integrity

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a third dimension (vertical stacking) to the traditional planar pad arrangement. By forming upper and lower pads at different vertical levels and connecting them through vertical interconnection wires, the design redistributes pads in three-dimensional space rather than extending wires horizontally across the backend, thus reducing wire length while maintaining redistribution capability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The pad arrangement is segmented into multiple groups (upper pads and lower pads) positioned at different vertical levels. This segmentation allows independent optimization of wire connections for each group, enabling shorter interconnection paths compared to a single-layer arrangement where all pads would require long horizontal connections

Inventive Principle:

Principle #1Segmentation

3Device complexity

If pads are arranged in a single layer, then the structure is simple, but the interconnection wire length increases

Engineering Contradiction:

Improvepad arrangement structureVSAvoidinterconnection wire length

Core Design Contradiction:

Device complexityVSLength of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional single-layer pad arrangement to a three-dimensional multi-layer structure. By utilizing vertical stacking with upper and lower pads at different heights, the design achieves shorter interconnection paths without significantly increasing structural complexity, as the multi-layer approach follows standard semiconductor fabrication techniques

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10665558B2Semiconductor memory including pads arranged in parallel

Publication Date: 2020.05.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.