3D Semiconductor Memory Device Vertical Pillar Bit Line Layout
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Solution Overview
Problem
The challenge in manufacturing low-cost, highly integrated three-dimensional semiconductor memory devices is the high cost and complexity of fine pattern forming technologies required for two-dimensional devices, which hinders the mass production of reliable 3D devices that match or exceed the performance of their 2D counterparts.
Innovation Solution
A semiconductor memory device design featuring a substrate with stacked word lines, vertically arranged pillars, and alternating bit lines, along with auxiliary lines that connect adjacent pillars with specific protrusions and angles, allowing for efficient electrical connections and reduced bending, thereby minimizing the need for expensive and complex equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern forming technologies are used to increase integration of two-dimensional semiconductor devices, then integration density is improved, but manufacturing cost and device complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked above each other, with word lines, bit lines, and charge storage structures arranged in vertical columns. This dimensional change allows significantly higher integration density without requiring proportionally more complex manufacturing equipment, as the stacking approach leverages vertical space rather than requiring ever-smaller lateral feature sizes.
2Quantity of substance
If expensive process equipment is used to produce very fine patterns for higher integration, then integration density is improved, but manufacturing cost becomes prohibitive
Solution Approach 1:
The memory device is divided into multiple discrete stacked layers, each containing memory cell transistors, charge storage structures, and interconnect lines. The segmentation into modular stacked units allows for standardized manufacturing processes that can be replicated, reducing the need for custom expensive equipment for each integration level. Each layer can be formed using relatively standard semiconductor processing techniques.
Solution Approach 2:
By moving to three-dimensional stacking, the patent achieves higher integration density through vertical arrangement rather than lateral scaling. This approach uses existing manufacturing capabilities more effectively, avoiding the need for extremely expensive next-generation lithography equipment that would be required to continue scaling two-dimensional devices to the same density levels.
3Quantity of substance
If three-dimensional memory structures are implemented to achieve high integration, then integration density is improved, but operational reliability becomes more difficult to ensure
Solution Approach 1:
The patent implements local quality by providing separate read and write verification paths for the three-dimensional memory structure. Read verification circuitry verifies data after read operations, while write verification circuitry verifies data after write operations. This localized verification at critical points in the 3D structure ensures operational reliability despite the increased complexity of vertical stacking and multiple interconnect layers.
Solution Approach 2:
The memory device incorporates verification circuitry that provides feedback on the success of read and write operations. The read verification unit verifies read data and generates verification signals, while the write verification unit verifies written data. This feedback mechanism allows for error detection and correction, ensuring reliable operation of the three-dimensional memory structure even as integration density increases.
Data Source
AI summary
A semiconductor memory device includes stacks on a substrate, each of the stacks including word lines stacked on the substrate and first and second string selection lines laterally spaced apart from each other, vertical pillars passing through the stacks, and first and second bit lines extending longitudinally in a first direction and alternatingly arranged in a second direction crossing the first direction. In a plan view, at least two adjacent ones of the first bit lines in the second direction and at least one of the second bit lines overlap each vertical pillar. A distance between a center of the vertical pillar and one of the first bit lines is different from that between the center of the vertical pillar and another of the first bit lines.