Semiconductor In-Memory Processing Without a Separate Bus
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in implementing in-memory processing due to the need for a separate bus and changes in the memory controller design, making it difficult to integrate with conventional systems.
Innovation Solution
A semiconductor device with a memory cell array, address and command input circuits, a processing control circuit, and a switch circuit that controls data paths based on address matching, allowing in-memory processing using conventional commands and avoiding the need for a separate bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate bus is provided for IMP commands, then in-memory processing capability is improved, but device complexity and system integration difficulty increase
Solution Approach 1:
The existing command and address bus is made multi-functional by enabling it to carry both conventional memory commands and IMP commands. The processing control circuit detects IMP commands through address matching against stored operand addresses, allowing the same bus infrastructure to support both traditional memory operations and in-memory processing without requiring additional dedicated buses.
Solution Approach 2:
The patent merges the IMP command transmission function into the existing command and address bus by combining the IMP command with operand addresses. This consolidation eliminates the need for a separate IMP command bus, reducing system complexity while maintaining full in-memory processing capability.
2Adaptability or versatility
If memory controller design is changed for IMP support, then in-memory processing is enabled, but ease of operation and compatibility with existing systems deteriorate
Solution Approach 1:
The memory device itself performs the IMP operation autonomously by detecting IMP commands through address matching and executing processing operations internally. The memory controller needs only to issue conventional read/write commands with specific addresses, and the device's processing control circuit handles the IMP logic, maintaining compatibility with existing controllers while enabling IMP functionality.
Solution Approach 2:
The command and address bus is made multi-functional by enabling it to carry both conventional memory commands and IMP commands. The processing control circuit detects IMP commands through address matching against stored operand addresses, allowing the same bus infrastructure to support both traditional memory operations and in-memory processing without requiring additional dedicated buses.
3Measurement precision
If address matching is performed in the processing control circuit, then in-memory processing accuracy is improved, but device complexity increases
Solution Approach 1:
Operand addresses are pre-loaded into the register array during initialization or setup phases. When an IMP command arrives, the processing control circuit simply compares the command address against these pre-stored addresses using straightforward matching logic, avoiding the need for complex real-time address resolution while maintaining high precision.
Data Source
AI summary
A semiconductor device includes a memory cell array, an address input circuit, a command input circuit, a data Input/Output (IO) circuit, a processing control circuit, a processing circuit, and a switch circuit. The processing control circuit includes a register array storing an address of an operand and determines whether an address provided from the address input circuit corresponds to the address stored in the register array. The processing circuit is configured to provide a processing result by performing an operation on data provided from the memory cell array. The switch circuit is configured to control a data path among the processing circuit, the data IO circuit, and the memory cell array and controls the data path to connect the memory cell array to the processing circuit when the address provided from the address input circuit corresponds to the address stored in the register array.