Semiconductor Memory Redundancy Repair via Priority-Based Failure Group Classification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration density in semiconductor devices leads to a decrease in fabrication yield due to failed memory cells, making it impossible to supply devices with even a single defective cell, despite efforts to improve yield through redundancy and error correction codes.
Innovation Solution
A semiconductor system comprising first and second semiconductor devices that classify failure groups of data, generate failure addresses, and perform error correction operations, replacing defective memory areas with redundancy areas based on priority, ensuring reliable data transmission and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If integration density is increased to improve device performance, then device performance is improved, but fabrication yield decreases due to increased failed memory cells
Solution Approach 1:
The memory array is divided into multiple banks, and failure groups are segmented by row and column addresses. This segmentation allows independent repair of specific failed regions without affecting the entire memory device, enabling high integration density while maintaining fabrication yield through targeted redundancy activation.
Solution Approach 2:
Redundancy memory cells and repair circuits are pre-configured within the semiconductor device structure. During fabrication, potential failure locations are identified and pre-mapped to redundancy resources, so that when failures occur, the repair can be automatically activated without requiring device rejection, thus maintaining high fabrication yield.
2Productivity
If redundancy memory cells are used to repair failed memory cells, then fabrication yield is improved, but device complexity increases
Solution Approach 1:
The redundancy memory cells are merged with the main memory array in a unified structure, sharing the same physical substrate and interconnect layers. The repair circuits are integrated within the memory device itself, combining diagnostic and repair functions with the memory storage function, thereby reducing overall device complexity while maintaining high fabrication yield.
Solution Approach 2:
The redundancy memory cells serve multiple functions: they can replace failed memory cells, provide additional storage capacity, and act as backup for entire memory banks. The repair circuits can handle various types of failures including stuck-at faults, bridging faults, and leakage faults, making the system universally applicable to different failure modes without increasing complexity.
3Reliability
If error correction codes are implemented to detect and correct errors, then data reliability is improved, but device complexity increases
Solution Approach 1:
The error correction system is self-service in that the memory device automatically detects, locates, and corrects errors using built-in redundancy cells and repair circuits. The system performs self-diagnosis during manufacturing and self-repair during operation without external intervention, improving data reliability while minimizing the need for complex external error correction hardware.
Solution Approach 2:
Instead of using complex mathematical error correction codes that require extensive computational resources, the system uses physical copying of data to redundancy memory cells. When a failure is detected, the data is copied from the failed cell to a corresponding redundancy cell, providing simple and efficient error correction with minimal added complexity.
Data Source
AI summary
A semiconductor system may be configured to classify failure groups of data including erroneous bits and may replace a memory area in which the failure groups are stored with a redundancy area. The replacement of the memory area in which the failure groups are stored, with the redundancy area, may be performed according to priorities of the failure groups.