3D Stacked Semiconductor Memory With Resistive Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electron charge control-based devices face limitations in performance, particularly in increasing integration density and reducing minimum feature size for phase-change memory devices, which are essential for next-generation memory devices with high capacity, ultra-high speed, and ultra-low power requirements.
Innovation Solution
A semiconductor memory device design featuring vertically formed word lines and parallel bit lines with unit memory cells, where each unit memory cell includes a switching device and a resistive device layer, allowing for adjustable integration density and reduced device size through controlled stacking of layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional electron charge control-based devices are used, then device performance is maintained at current levels, but integration density and minimum feature size reduction are limited
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a three-dimensional stacked architecture where bit lines are vertically stacked between word lines. This vertical stacking enables multiple memory cells to occupy the same footprint area on the substrate, dramatically increasing integration density without further reducing minimum feature size in the lateral plane.
Solution Approach 2:
The patent implements a nested structure where bit lines are positioned between word lines in a stacked configuration, with unit memory cells formed at the intersections of these stacked lines. This nesting arrangement allows multiple conductive lines to occupy overlapping spatial regions, effectively multiplying the number of addressable memory cells within a given device area.
2Quantity of substance
If phase-change memory devices are developed for next-generation requirements, then high capacity and ultra-low power are achieved, but reduction in minimum feature size remains difficult due to light source technical limits
Solution Approach 1:
The patent employs vertical stacking of bit lines and word lines to create a three-dimensional memory architecture. This approach increases storage capacity by multiplying the number of memory cells per unit area through vertical layering, bypassing the need to further reduce lateral feature sizes which are constrained by light source resolution in phase-change material patterning.
Solution Approach 2:
The patent divides the memory device into multiple stacked layers with bit lines segmented into separate vertical stacks between pairs of word lines. This segmentation allows independent formation and addressing of memory cells in each stack, enabling capacity scaling through increased layer count rather than lateral dimension reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration density and reduces device size, enabling improved performance and capacity in semiconductor memory devices while maintaining ultra-high speed and low power consumption.
Implementation Method 1
A source for providing heat to a phase-change material may be current, where an amount of heat applied to the phase-change material depends on the intensity of the supplied current and the time that the current is supplied.
Implementation Method 2
Phase-change memory devices often use a phase-change material as a resistive medium, where a phase-change material switches between a crystalline state and an amorphous state in response to heat.
Data Source
AI summary
A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.