3D Semiconductor Memory Stacking via Sacrificial Layer Etching
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor memory devices faces challenges in reducing manufacturing complexity and improving operational reliability, particularly in the stacking and connection of memory cells and layers, which affects the overall performance and reliability of the device.
Innovation Solution
A method involving the sequential stacking of a source sacrificial layer, an upper protective layer, and an etch stop layer, followed by alternately stacking interlayer dielectric layers and gate sacrificial layers, forming slits to replace these sacrificial layers with conductive patterns and source layers, ensuring proper spacing and insulation for improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sacrificial layers are used to form channel layers and source/drain structures, then manufacturing complexity is reduced, but operational reliability may be compromised due to potential malfunctions in stacked structures
Solution Approach 1:
The patent introduces protective layers as intermediary elements between the sacrificial layers and the final device structure. These protective layers prevent direct contact between potentially harmful sacrificial materials and functional regions, thereby maintaining manufacturing simplicity while ensuring operational reliability through isolation and protection of critical structures.
Solution Approach 2:
The patent extracts and removes sacrificial layers after they have served their purpose in defining channel and source/drain structures. By completely removing these temporary structures through carefully designed etch processes, the patent eliminates potential reliability issues while maintaining the manufacturing advantages of using sacrificial materials during fabrication.
2Quantity of substance
If multiple layers are stacked to form three-dimensional memory cells, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning and protection steps before final layer stacking. By pre-defining the locations and shapes of channel layers, source/drain structures, and gate electrodes using sacrificial and protective layers, the patent establishes precise alignment references that guide subsequent stacking operations, thereby maintaining high integration density with controlled precision requirements.
Solution Approach 2:
The patent divides the three-dimensional memory structure into distinct functional segments (channel layers, source/drain structures, gate electrodes, interlayer dielectric layers) that can be independently formed and positioned. This segmentation allows each layer to be optimized and positioned separately, reducing the cumulative precision errors that would occur in monolithic stacking while achieving high integration density.
3Manufacturing precision
If etch stop layers are used to control etching depth, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent designs the etch stop layer to serve multiple functions: it acts as an etching depth reference, a structural support layer, and a defining boundary for channel layer formation. By making this single layer multi-functional, the patent achieves precise etching control without proportionally increasing device complexity, as the same layer structure provides multiple critical functions simultaneously.
Data Source
AI summary
A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.