Semiconductor Memory Device Schottky Junction Reliability

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Solution Overview

Problem

Current three-dimensional semiconductor memory devices face challenges in achieving high integration density and operational reliability, particularly in portable electronic devices where large capacity and portability are required.

Innovation Solution

The semiconductor memory device incorporates a stack structure with a channel layer passing through it, surrounded by a memory layer, and includes source and drain select gates that form Schottky junctions with the channel layer, enhancing operational reliability and speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensional semiconductor memory devices are used to increase integration density, then storage capacity is improved, but manufacturing complexity and achieving operational reliability become more difficult

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures by stacking multiple memory layers and select gates in the vertical dimension. This allows significantly increased storage capacity within the same footprint area while maintaining manufacturability through standardized vertical stacking processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is segmented into multiple functional layers including channel layers, memory layers, source select gates, and drain select gates stacked vertically. Each layer performs a specific function, allowing independent optimization and simplifying the manufacturing process by enabling modular fabrication of complex three-dimensional structures.

Inventive Principle:
Principle #1Segmentation

2Speed

If Schottky junctions are formed between channel layer and select gates, then operating speed is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveoperating speedVSAvoidjunction formation precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent forms Schottky junctions by carefully selecting and controlling the work function parameters of the select gate materials relative to the channel layer. By adjusting material composition and thickness parameters during fabrication, the Schottky barrier characteristics are optimized to achieve high operating speed while maintaining manufacturability through parameter control rather than requiring extreme geometric precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the operating speed and reliability of the semiconductor memory device by forming Schottky junctions between the channel layer and select gates, enabling efficient data storage and retrieval.

Implementation Method 1

the channel layer and the source select gate form a Schottky junction, and the channel layer and the drain select gate form a Schottky junction

Methodology Applied
Scientific EffectSchottky junction: Diode

Data Source

PatentUS11309436B2Semiconductor memory device
Publication Date: 2022.04.19 SK HYNIX INC
  • US11309436B2 patent drawing
  • US11309436B2 patent drawing
  • US11309436B2 patent drawing

AI summary

A semiconductor memory device includes, a stack structure, and a channel structure passing through the stack structure, wherein the channel structure includes a channel layer passing through the stack structure and a memory layer surrounding the channel layer, the stack structure includes a gate contacting the channel layer, and the channel layer and the gate form a Schottky junction.