Semiconductor Memory Device with Segmented Crystal Grain Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional semiconductor memory devices face challenges in reducing voltage drop and maintaining uniform film quality due to uneven crystal grain sizes and film thicknesses in their semiconductor layers, which can lead to issues with setting memory cells and select gate transistors to the correct states.
Innovation Solution
The semiconductor memory device employs a semiconductor layer with distinct portions having different film thicknesses and crystal grain sizes, where the first portion has a larger crystal grain width than its film thickness and the second portion has a smaller crystal grain width, and includes a metal silicide layer between these portions, formed using a Metal Induced Lateral Crystallization (MILC) method to control crystallization progress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor layer with uniform structure is used, then the manufacturing process is simple, but the voltage drop increases and film quality becomes non-uniform due to uneven crystal grain sizes
Solution Approach 1:
The semiconductor layer is divided into multiple regions with different crystal grain sizes: a first region with larger crystal grains and a second region with smaller crystal grains. This segmentation allows each region to contribute differently to device performance, with larger grains reducing voltage drop and smaller grains providing uniform film quality control.
Solution Approach 2:
Different regions of the semiconductor layer are given different local properties through controlled crystal grain sizes. The first region has larger crystal grains optimized for reducing voltage drop, while the second region has smaller crystal grains optimized for film quality uniformity. This local differentiation resolves the contradiction between voltage drop and film quality.
2Reliability
If the semiconductor layer has large crystal grains to reduce voltage drop, then voltage drop decreases, but film quality uniformity deteriorates
Solution Approach 1:
The semiconductor layer is segmented into regions with different crystal grain sizes to simultaneously achieve low voltage drop and uniform film quality. The first region with larger grains addresses voltage drop, while the second region with smaller grains addresses film quality uniformity.
Solution Approach 2:
Each region is optimized with appropriate crystal grain size for its specific function. Larger grains in the first region reduce voltage drop, while smaller grains in the second region ensure uniform film quality, allowing both requirements to be satisfied through local optimization.
3Manufacturing precision
If MILC method is used to control crystallization, then crystal grain size distribution is improved, but the manufacturing process complexity increases
Solution Approach 1:
The MILC method controls crystallization by changing key parameters including temperature profiles and metal catalyst distribution. By adjusting these parameters, the process achieves precise control over crystal grain size distribution in different regions, improving manufacturing precision despite increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces voltage drop and maintains uniform characteristics across the semiconductor layer, preventing issues with setting memory cells and select gate transistors to the correct states, while ensuring efficient data storage and retrieval.
Implementation Method 1
a gate insulating layer provided between the control gate electrode and semiconductor layer and capable of accumulating a charge
Implementation Method 2
formed using a Metal Induced Lateral Crystallization (MILC) method to control crystallization progress
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The semiconductor layer comprises: a first portion extending in the first direction and facing a plurality of the control gate electrodes; and a second portion provided on a closer side to the substrate than this first portion. A film thickness of the first portion in the second direction is larger than a film thickness of the second portion in the second direction. A crystal grain included in the first portion is larger than a crystal grain included in the second portion.