Semiconductor Memory Device with Segmented Plug Structure
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Solution Overview
Problem
The challenge in developing electronic devices is to improve the integration and fabrication of variable resistance elements, particularly in resistive random access memory (RRAM), where high alignment clearance between contact plugs and lines can lead to bridge failures, necessitating enhanced processes for forming semiconductor memory devices with improved alignment and simplified patterning.
Innovation Solution
The proposed solution involves a semiconductor memory device design with specific configurations, including lower and upper plugs, lines, insulation patterns, and variable resistance elements, where the alignment clearance is improved, and the aspect ratio of upper plugs is lowered, simplifying the patterning process and reducing the difficulty of forming upper plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high alignment clearance is used between contact plugs and lines, then bridge failures are reduced, but device area increases and integration density decreases
Solution Approach 1:
The patent transitions from planar alignment to three-dimensional alignment by forming upper plugs that extend vertically from lower plugs through multiple interlayer dielectric layers. This vertical dimension allows alignment clearance to be achieved in the Z-direction rather than requiring increased lateral spacing in the X-Y plane, thus preventing bridge failures without increasing device area.
Solution Approach 2:
The structure employs nested plugs where upper plugs are positioned within and aligned with lower plugs across multiple layers. This nesting arrangement concentrates the alignment clearance requirement into the vertical stacking region rather than spreading it laterally, allowing compact integration while maintaining reliable electrical connections.
2Manufacturing precision
If complex patterning processes are used to form upper plugs, then alignment precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
Lower plugs are formed first as pre-positioned alignment references before forming upper plugs. This preliminary action establishes a fixed alignment baseline that simplifies subsequent upper plug patterning, as the upper plugs can be aligned to the existing lower plug structures rather than requiring complex multi-step alignment procedures.
Solution Approach 2:
Interlayer dielectric layers serve as intermediary structures between lower and upper plugs. These dielectric layers provide a fabrication-friendly medium that allows upper plugs to be formed with simplified patterning while maintaining precise alignment through the vertical stacking process, avoiding the need for complex lateral alignment procedures.
3Length of moving object
If upper plugs have high aspect ratio, then vertical integration is achieved, but fabrication difficulty and yield decrease
Solution Approach 1:
The plug structure is segmented into multiple lower plugs and upper plugs separated by interlayer dielectric layers. This segmentation breaks down what would otherwise be a single high aspect ratio plug into multiple shorter plug segments, each with more manageable aspect ratios that are easier to fabricate with higher yield while achieving the same overall vertical integration.
Solution Approach 2:
The plug structure utilizes the vertical dimension by stacking multiple lower and upper plugs through interlayer dielectric layers. This vertical stacking approach achieves high integration in the Z-direction without requiring each individual plug to have an excessively high aspect ratio, as the total height is distributed across multiple shorter plug segments.
Data Source
AI summary
An electronic device includes a semiconductor memory. The semiconductor memory includes first and second lower plugs, a first pad, a second pad, a first lower line, a second lower line, a first insulation pattern, a second insulation pattern, an upper plug, an upper line, and a plurality of variable resistance elements disposed at regions where the first and second lower lines overlap the upper line.