Semiconductor Memory Device Serial Signal Conversion
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing the number of bits of signals outputted from control logic during operations, leading to increased complexity and reduced integration density due to the high number of wires required for transmitting N-bit encoding signals.
Innovation Solution
A semiconductor memory device design that includes a control logic to convert parallel N-bit encoding signals into a serial 1-bit data signal, which is then used to generate internal address signals and an internal clock signal, reducing the number of wires needed to transmit signals to the decoder circuit and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel N-bit encoding signals are transmitted from control logic to decoder circuit, then the decoder can switch operating voltages according to the encoding signals, but the number of wires required increases leading to increased complexity and reduced integration density
Solution Approach 1:
The N-bit parallel encoding signals are segmented and transmitted sequentially in time-divided manner through a single wire. The control logic divides the transmission into N time slots, with each bit transmitted in sequence, eliminating the need for N parallel wires while maintaining the decoder's ability to reconstruct and use the full N-bit encoding signals for reliable operation voltage switching
Solution Approach 2:
The patent transforms the spatial dimension (parallel wires) into the temporal dimension (sequential transmission). By transmitting N-bit data across one wire over N time periods using time-division multiplexing, the invention converts a spatial complexity problem into a temporal sequencing problem, reducing wire count while preserving data integrity for decoder operation
2Reliability
If parallel N-bit encoding signals are transmitted from control logic to decoder circuit, then the decoder can switch operating voltages according to the encoding signals, but the number of wires required increases leading to reduced integration density
Solution Approach 1:
The N-bit parallel signal is segmented into sequential time slots for transmission over a single wire. This segmentation allows the same amount of data to be transmitted with far fewer physical connections, directly improving integration density by freeing up wire resources and reducing the area required for signal routing between control logic and decoder circuit
Solution Approach 2:
By moving from spatial parallelism to temporal sequencing, the invention dramatically reduces the area occupied by interconnect wires. The single-wire sequential transmission approach eliminates the need for N parallel wire paths, thereby increasing the available area for other circuit elements and improving overall integration density
3Device complexity
If parallel N-bit encoding signals are converted to serial 1-bit data signal, then the number of wires is reduced and integration density is improved, but additional conversion circuitry is required
Solution Approach 1:
The control logic unit is designed to perform multiple functions: it generates the N-bit encoding signals, converts them to serial 1-bit data streams, manages time-division multiplexing, and controls the sequencing. By consolidating these functions into a single multi-functional control logic unit, the patent avoids adding separate dedicated conversion circuits, thereby maintaining ease of manufacture while achieving wire reduction
Solution Approach 2:
The patent merges the parallel-to-serial conversion function with the existing control logic unit rather than implementing it as a separate circuit module. This consolidation integrates the conversion capability into the control logic's existing architecture, reducing the total component count and simplifying the manufacturing process while still achieving the wire reduction benefits
Data Source
AI summary
Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.