Semiconductor Memory Cell Area Reduction via Shared Source Regions
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Solution Overview
Problem
Conventional semiconductor memory devices require larger memory cell areas due to the need for separate source and deletion regions for each memory cell, which increases the overall size and reduces the density of memory cells.
Innovation Solution
The semiconductor device design shares source and deletion regions among multiple memory cells, with selection and floating gates extending at angles to the word line direction, allowing for a more compact layout by overlapping these regions and reducing the area required for each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate source regions and deletion regions are provided for each memory cell, then the memory cell can function properly with adequate spacing, but the memory cell area increases
Solution Approach 1:
The patent merges source regions and deletion regions that were previously separate for each memory cell into shared common regions. Multiple memory cells (first, second, third, and fourth memory cells) share the same source signal line and deletion signal line, eliminating the need for individual source and deletion regions in each cell. This consolidation reduces the overall memory cell area while maintaining proper functionality through shared infrastructure.
Solution Approach 2:
The patent implements universal signal lines that serve multiple memory cells simultaneously. The source signal line functions as a common source region for multiple memory cells, and the deletion signal line serves as a common deletion region. This multi-functional approach allows the same physical region to support multiple memory cell operations, thereby reducing the total area required.
2Ease of manufacture
If selection gate and floating gate extend in the same direction as word line, then the layout is simple and manufacturing is easier, but the memory cell area increases
Solution Approach 1:
The patent changes the orientation of the selection gate and floating gate from extending in the same direction as the word line (horizontal) to extending in a direction different from the word line direction (vertical or diagonal). This dimensional reorientation allows the gates to overlap with shared source and deletion regions more effectively, reducing the horizontal spread of each memory cell while maintaining proper electrical connections and functionality.
Data Source
AI summary
First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction.