3D Semiconductor Memory Integration via Stacked Channel Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of memory cells in two-dimensional semiconductor devices is limited, necessitating the development of three-dimensional memory elements with stacked memory cells to enhance operational reliability, which requires innovative structural and manufacturing methods to achieve stable and efficient memory storage.
Innovation Solution
A semiconductor device structure featuring alternately stacked conductive and insulating layers, separation insulating structures, channel layers, and gate insulating layers, along with a manufacturing method that includes forming sacrificial layers, separation insulating structures, and channel layers to create a stable and integrated memory string configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory cell integration is used, then manufacturing process is simple, but integration degree is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell layout to three-dimensional stacked structure. Memory cells are arranged in multiple layers vertically (first memory cell layer, second memory cell layer, etc.) stacked on the substrate, enabling significant increase in integration density while maintaining manufacturability through systematic layer-by-layer fabrication processes.
Solution Approach 2:
The memory device is divided into multiple functional layers including substrate, first memory cell layer, second memory cell layer, bit lines, word lines, and select gates. Each layer performs specific functions and can be manufactured independently through sequential processing steps, allowing complex 3D integration while keeping individual manufacturing steps manageable.
2Quantity of substance
If three-dimensional stacked memory cells are used, then integration degree increases, but structural stability becomes difficult to maintain
Solution Approach 1:
The patent employs composite material structures combining conductive materials (for electrodes and interconnects), insulating materials (for isolation and gate dielectrics), and semiconductor materials (for memory cell transistors). This multi-material approach enables complex 3D stacking while maintaining structural integrity through appropriate material selection and layer configuration.
Solution Approach 2:
The manufacturing process forms sacrificial layers and sacrificial spacers before final structure formation. These preliminary structures guide the self-aligned formation of channel layers and gate structures, ensuring precise positioning and structural stability of the stacked memory cells without requiring complex alignment steps.
3Stability of the object's composition
If complex manufacturing methods are used to achieve stable 3D structure, then structural stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs self-aligned manufacturing processes where sacrificial layers and spacers automatically define the positions of channel layers and gate structures. The sacrificial spacers formed on sacrificial layers serve as templates for subsequent etching and deposition steps, eliminating the need for separate alignment operations and reducing manufacturing complexity despite the 3D structure.
Solution Approach 2:
Sacrificial layers and sacrificial spacers are formed in advance to establish precise geometric relationships between stacked components. These preliminary structures enable self-aligned formation of memory cell layers, bit lines, and word lines, simplifying the overall manufacturing process while ensuring structural stability of the three-dimensional configuration.
Data Source
AI summary
A semiconductor device including: a stack including first conductive layers and insulating layers that are alternately stacked; and second conductive layers disposed on the stack; a separation insulating structure disposed on the stack and configured to insulate the second conductive layers from each other; first channel layers passing through the stack; memory layers enclosing sidewalls of the first channel layers; second channel layers disposed on the stack and passing through the second conductive layers, and each having a width less than a width of the first channel layers; gate insulating layers enclosing sidewalls of the second channel layers; and third channel layers configured to respectively couple the first channel layers with the second channel layers and extending into the second channel layers.