Semiconductor Memory Stacked Gate Structure Suppressing Short-Channel Effect
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Solution Overview
Problem
As semiconductor memory technology advances, the short-channel effect increases due to decreasing gate length and width, leading to threshold fluctuation, weakened control power, and elevated contact resistance, making it difficult to maintain sufficient storage capacity and control over memory cell transistors.
Innovation Solution
The semiconductor memory design incorporates a buried insulating film, a floating gate electrode layer, and a method of forming trenches to create a stacked gate structure with alternating isolation insulating films, allowing for increased floating gate volume and improved gate control, thereby reducing threshold fluctuation and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate length and gate width are decreased to increase integration density, then the storage capacity increases, but the short-channel effect increases causing threshold fluctuation and weakened gate control
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional side-wall gate control. The gate electrode is positioned on the side wall of the insulating film rather than above the channel, creating a vertical field effect that dominates over the horizontal short-channel effects. This dimensional change allows effective gate control even with reduced gate length and width.
Solution Approach 2:
The gate electrode is nested within the trench structure formed by the insulating film. The insulating film forms a cavity that contains the gate electrode, creating a nested configuration where the gate is embedded in the insulating material. This nesting provides electrostatic shielding and enhances the gate's control over the channel while reducing sensitivity to dimensional variations.
2Reliability
If the channel region is thinned to improve pinch-off characteristic, then the short-channel effect is suppressed, but the contact area for etching penetration is insufficient causing elevated contact resistance
Solution Approach 1:
The patent moves the gate control from horizontal planar geometry to vertical side-wall geometry. By forming the gate electrode on the side wall of the insulating film, the effective gate control area increases in the vertical dimension while the horizontal channel thickness can be reduced for better pinch-off. This dimensional transition decouples the trade-off between channel thickness and contact area.
Solution Approach 2:
The insulating film is formed with sufficient thickness before thinning the channel region. This preliminary formation of a thick insulating film ensures that adequate contact area is available for subsequent etching processes, and the gate electrode is then formed on the side wall of this pre-formed insulating structure, allowing channel thinning without compromising contact characteristics.
Data Source
AI summary
A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction.