3D Semiconductor Memory Device Vertical Integration
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost and practicality of expensive processing equipment needed to form fine patterns, hindering further increases in performance and density.
Innovation Solution
A three-dimensional semiconductor memory device design featuring vertically stacked semiconductor patterns and conductive lines with stepwise structures on contact regions, along with a peripheral transistor connected to these structures, enhances integration without requiring expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If expensive processing equipment is used to form fine patterns, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional stacked structures. By stacking multiple semiconductor layers vertically, the invention achieves higher integration density without requiring finer lateral patterns, thus avoiding the need for expensive processing equipment while maintaining manufacturing precision.
2Quantity of substance
If two-dimensional planar device integration is increased, then device density is improved, but the area occupied by unit memory cell increases
Solution Approach 1:
The invention stacks multiple semiconductor layers in the vertical direction (third dimension) to increase device density. This allows multiple memory cells to be stacked vertically, achieving higher integration without increasing the lateral footprint of each unit memory cell, thus resolving the contradiction between density and area.
Solution Approach 2:
The patent implements a stacked structure where multiple semiconductor layers are nested vertically, with each layer containing memory cells that share common bit lines and word lines. This nesting approach increases the quantity of storage elements within the same planar area, improving device density without proportionally increasing unit cell area.
3Quantity of substance
If three-dimensional stacked structures are implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete stacked layers, each with defined functional regions (cell regions, contact regions, peripheral circuit regions). This segmentation allows for modular manufacturing and assembly, reducing the overall manufacturing complexity despite the increased integration density achieved through stacking.
Solution Approach 2:
The stacked structure employs shared bit lines and word lines that serve multiple memory cells across different layers. This multi-functionality reduces the total number of interconnect lines required, thereby reducing manufacturing complexity while maintaining high integration density.
Data Source
AI summary
A semiconductor memory device comprising a substrate including a cell region, first and second contact regions, and a bit peripheral circuit region disposed between the first and second contact regions. A first stack structure is disposed on the cell region and the first contact region. A second stack structure is disposed on the cell region and the second contact region. A peripheral transistor is disposed on the bit peripheral circuit region and is electrically connected to the first and second stack structures. Each of the first and second stack structures comprises semiconductor patterns vertically stacked on the cell region, and conductive lines having connection with the semiconductor patterns and extending along a first direction from the cell region onto corresponding first and second contact regions. The conductive lines have stepwise structures on the first and second contact regions.