3D Semiconductor Memory Device With Stopper Layer For Uniformity
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the high cost of advanced pattern fineness technologies, necessitating the development of three-dimensional semiconductor memory devices with improved electrical and reliability characteristics.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack of layers on a substrate, featuring bit lines, semiconductor patterns, gate electrodes, vertical insulating layers, stopper layers, and data storing elements, where the stopper layer ensures uniformity in the length of semiconductor patterns and electrodes, enhancing electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use advanced pattern fineness technology to increase integration, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked vertically, with bit lines extending in a first direction and semiconductor patterns extending in a second direction crossing the first direction. This dimensional transition allows significant increase in integration density without requiring further reduction in pattern size, thereby avoiding the exponential cost increase associated with advanced lithography processes.
2Ease of manufacture
If three-dimensional semiconductor memory devices are designed with varied electrode widths, then manufacturing flexibility improves, but electrical performance uniformity deteriorates
Solution Approach 1:
The patent applies different width characteristics to different portions of the first electrode based on local requirements. The first portion adjacent to the stopper layer has a smaller largest width in the first direction, while the second portion extended from the first portion has a larger largest width. This local differentiation optimizes both manufacturing flexibility and electrical performance uniformity by providing appropriate dimensions for each functional region.
3Reliability
If the first portion of the first electrode is made narrower than the second portion, then device reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates a stopper layer positioned adjacent to the first portion of the first electrode before electrode formation. This stopper layer serves as a pre-established reference structure that defines the boundary and dimensions of the first portion. By having this reference structure in place beforehand, the subsequent formation of the first electrode with varied widths can be achieved with standard manufacturing precision, avoiding the need for extremely precise direct patterning of the narrowed section.
Data Source
AI summary
A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.