Semiconductor Memory Device with Tilted Side Wall Charge Retention
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in downsizing due to non-uniform thickness of the gate insulating film, which can lead to dielectric breakdown and leakage of current, and interference between charge retention sections during re-programming actions.
Innovation Solution
A method of manufacturing a semiconductor memory device with charge retention sections located partially lower than the interface between the gate insulating film and the channel region, using a tilted side wall for the opening beneath the gate insulating film to ensure uniform thickness of the first insulating film, and employing a three-film construction with silicon nitride and silicon oxide films to inhibit charge leakage and enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate insulating film thickness is reduced for downsizing, then the memory device size is reduced, but dielectric breakdown and current leakage occur due to non-uniform thickness
Solution Approach 1:
The patent positions charge retention sections in three-dimensional space, specifically located partially lower than the interface between the gate insulating film and channel region. This vertical positioning in the depth dimension allows the gate insulating film to maintain sufficient thickness at the surface interface for reliability while enabling overall device downsizing through efficient spatial utilization.
Solution Approach 2:
The patent creates local quality differentiation by positioning charge retention sections at specific vertical locations (partially lower than the gate insulating film interface) rather than uniformly distributing them. This localized placement optimizes the gate insulating film thickness distribution, ensuring sufficient thickness where needed while reducing overall device dimensions.
2Area of stationary object
If charge retention sections are positioned closer together for downsizing, then device area is reduced, but interference between sections occurs during re-programming actions
Solution Approach 1:
The patent resolves interference issues by utilizing the vertical dimension for charge retention section placement. By positioning sections partially lower than the gate insulating film interface, the invention creates sufficient vertical separation that prevents lateral interference during re-programming operations, enabling closer horizontal spacing for downsizing.
Solution Approach 2:
The patent segments the charge retention sections into distinct vertical zones, with each section positioned at specific depths relative to the gate insulating film interface. This segmentation isolates the electrical fields of adjacent sections, preventing interference during re-programming while allowing compact horizontal arrangement.
3Productivity
If the gate insulating film is made thinner for higher integration, then manufacturing precision requirements increase, but non-uniform thickness leads to dielectric breakdown
Solution Approach 1:
The patent addresses manufacturing precision challenges by creating local quality variations in the gate insulating film structure. By positioning charge retention sections partially lower than the interface, the invention ensures sufficient film thickness at critical surface regions while allowing thinner regions elsewhere, thereby maintaining high integration density without dielectric breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves improved operational reliability, reduced power consumption, and efficient data storage with minimized short channel effects, allowing for effective downsizing while preventing dielectric breakdown and interference between charge retention sections.
Implementation Method 1
The gate insulating film comprises so-called an ONO film (silicon oxide film/silicon nitride film/silicon oxide film) where a silicon nitride film is sandwiched between two silicon oxide films
Implementation Method 2
a pair of charge retention sections of a side wall spacer form provided on both sides of the gate electrode and the gate insulating film for memory of two-bit data
Implementation Method 3
a fourth step of depositing a first insulating film which covers the side and bottom surface of the opening
Data Source
AI summary
A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which the bottom is located below the interface between the active region and the gate insulating film and then providing a gate electrode between the openings, depositing a first insulating film which covers the side and bottom surface of the opening, depositing a second insulating film over the first insulating film, shaping the first and second insulating films into a side wall spacer shape by etching to provide charge retention sections beside the gate electrode and providing diffusion areas at opposite sides of the gate electrode beneath the charge retention sections in the active region.