3D Semiconductor Memory Charge Trapping Structure
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining optimal electrical connections and preventing electrical division of the semiconductor layer acting as a channel, leading to fluctuations in threshold voltage during read and write operations, especially when using a charge accumulation layer positioned inside the substrate.
Innovation Solution
The semiconductor memory device design positions the lower end of the charge accumulation layer between the stacked portions of the control gate electrodes and the semiconductor layer, preventing electrical division and maintaining stable channel operation by integrating the semiconductor layer with the substrate and using a specific layer structure that avoids the charge accumulation layer on the substrate's inside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the charge accumulation layer is positioned inside the substrate, then the integration level is improved, but electrical division of the semiconductor layer occurs causing threshold voltage fluctuation
Solution Approach 1:
The patent transitions from a planar charge accumulation layer to a three-dimensional charge trapping structure formed on the sidewalls of trenches. This vertical dimensionality change allows the charge accumulation function to be maintained while eliminating the electrical division problem by positioning the charge trapping regions laterally separated from the channel-forming semiconductor layer.
Solution Approach 2:
The charge accumulation layer is segmented into multiple discrete charge trapping regions formed in separate trenches. This segmentation spatially separates the charge accumulation function from the channel region, preventing electrical division while maintaining high integration density through vertical stacking of multiple such structures.
2Quantity of substance
If the charge accumulation layer is positioned inside the substrate, then capacity is increased, but electrical connection stability deteriorates
Solution Approach 1:
The patent utilizes vertical trenches extending into the substrate to create three-dimensional charge trapping regions. This approach increases data capacity by adding vertical stacking dimensions while maintaining stable electrical connections through proper lateral spacing and isolation of the charge trapping regions from the channel structures.
Solution Approach 2:
The patent introduces insulating layers and isolation structures as intermediaries between the charge accumulation regions and the semiconductor channel. These intermediary elements prevent direct electrical interaction that would cause threshold voltage fluctuation while allowing the charge trapping structures to maintain their data storage function.
3Productivity
If three-dimensional memory cell structure is used, then integration level is raised, but manufacturing complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into repeating modular units consisting of trenches, charge trapping regions, and channel structures. This modular segmentation simplifies manufacturing by allowing standardized fabrication processes to be applied repeatedly across the wafer, reducing overall manufacturing complexity despite the increased integration density.
Solution Approach 2:
The patent designs the three-dimensional structure with multi-functional elements where the same trench structure serves both as an isolation region and as a container for charge trapping. This universality reduces the total number of separate fabrication steps and materials required, thereby reducing manufacturing complexity while maintaining high integration.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.