3D Semiconductor Memory Vertical Pattern Geometry
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the high cost of advanced pattern forming technologies, which restricts their ability to achieve higher integration density and faster operation speeds while maintaining affordability.
Innovation Solution
A semiconductor device with a three-dimensional memory array structure, featuring vertically stacked patterns arranged in specific geometric configurations to increase integration density and operation speed, including a substrate with electrode structures and vertical patterns that form regular and scalene triangles, and subsidiary lines connecting these patterns to bit lines, allowing for efficient use of space and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use advanced pattern forming technology to increase integration density, then integration density is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell structures to three-dimensional vertical structures. Memory cells are stacked vertically with multiple levels, allowing integration density to increase without requiring proportionally smaller lateral feature sizes. This dimensional change enables higher capacity while avoiding the need for extremely expensive advanced lithography processes.
Solution Approach 2:
The patent implements nested structures where multiple memory cell layers are stacked vertically, with each layer containing complete transistor and capacitor structures. The vertical stacking allows multiple functional layers to be nested within a compact footprint, achieving high integration density through vertical consolidation rather than lateral scaling.
2Quantity of substance
If two-dimensional semiconductor memory devices increase integration by reducing unit cell area, then integration density is improved, but operation speed deteriorates
Solution Approach 1:
By moving to three-dimensional vertical structures, the patent achieves higher integration density without compressing the lateral dimensions of individual memory cells. The vertical stacking allows sufficient lateral space to be maintained for optimal transistor and capacitor sizing, preserving operation speed while increasing capacity through the third dimension.
3Area of stationary object
If vertical patterns are arranged in regular triangle configurations, then space utilization is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent employs both regular and irregular (scalene) triangle arrangements of vertical patterns. The irregular arrangements break the symmetry and complexity of the patterning process, allowing for more flexible and manufacturable structures while still achieving high space utilization. This asymmetric approach simplifies the manufacturing process compared to strictly regular patterns.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes an electrode disposed on a substrate and a plurality of vertical patterns passing through the electrode. The vertical patterns include first vertical patterns arranged to form a rhombus and second vertical patterns arranged to form a non-regular trapezoid or a rhombus.